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[u-boot] / board / freescale / common / ns_access.c
1 /*
2  * Copyright 2014 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <fsl_csu.h>
10 #include <asm/arch/ns_access.h>
11 #include <asm/arch/fsl_serdes.h>
12
13 void set_devices_ns_access(unsigned long index, u16 val)
14 {
15         u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
16         u32 *reg;
17         uint32_t tmp;
18
19         reg = base + index / 2;
20         tmp = in_be32(reg);
21         if (index % 2 == 0) {
22                 tmp &= 0x0000ffff;
23                 tmp |= val << 16;
24         } else {
25                 tmp &= 0xffff0000;
26                 tmp |= val;
27         }
28
29         out_be32(reg, tmp);
30 }
31
32 static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
33 {
34         int i;
35
36         for (i = 0; i < num; i++)
37                 set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
38 }
39
40 void enable_layerscape_ns_access(void)
41 {
42 #ifdef CONFIG_ARM64
43         if (current_el() == 3)
44 #endif
45                 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
46 }
47
48 void set_pcie_ns_access(int pcie, u16 val)
49 {
50         switch (pcie) {
51 #ifdef CONFIG_PCIE1
52         case PCIE1:
53                 set_devices_ns_access(CSU_CSLX_PCIE1, val);
54                 set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
55                 return;
56 #endif
57 #ifdef CONFIG_PCIE2
58         case PCIE2:
59                 set_devices_ns_access(CSU_CSLX_PCIE2, val);
60                 set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
61                 return;
62 #endif
63 #ifdef CONFIG_PCIE3
64         case PCIE3:
65                 set_devices_ns_access(CSU_CSLX_PCIE3, val);
66                 set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
67                 return;
68 #endif
69         default:
70                 debug("The PCIE%d doesn't exist!\n", pcie);
71                 return;
72         }
73 }