2 * Copyright 2006,2010 Freescale Semiconductor
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #define pixis_base (u8 *)PIXIS_BASE
34 void pixis_reset(void)
36 out_8(pixis_base + PIXIS_RST, 0);
42 * Per table 27, page 58 of MPC8641HPCN spec.
44 static int set_px_sysclk(unsigned long sysclk)
46 u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
98 printf("Unsupported SYSCLK frequency.\n");
102 vclkh = (sysclk_s << 5) | sysclk_r;
105 out_8(pixis_base + PIXIS_VCLKH, vclkh);
106 out_8(pixis_base + PIXIS_VCLKL, vclkl);
108 out_8(pixis_base + PIXIS_AUX, sysclk_aux);
113 /* Set the CFG_SYSPLL bits
115 * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
116 * read_from_px_regs() is called.
118 static int set_px_mpxpll(unsigned long mpxpll)
129 clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
133 printf("Unsupported MPXPLL ratio.\n");
137 static int set_px_corepll(unsigned long corepll)
161 printf("Unsupported COREPLL ratio.\n");
165 clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
169 #ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
170 #define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
173 /* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
175 * The PIXIS can be programmed to look at either the on-board dip switches
176 * or various other PIXIS registers to determine the values for COREPLL,
177 * MPXPLL, and SYSCLK.
179 * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
180 * register that tells the pixis to use the various PIXIS register.
182 static void read_from_px_regs(int set)
184 u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
187 tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
189 tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
191 out_8(pixis_base + PIXIS_VCFGEN0, tmp);
194 /* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
195 * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
197 #ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
198 #define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
201 /* Configure the source of the boot location
203 * The PIXIS can be programmed to look at either the on-board dip switches
204 * or the PX_VBOOT[LBMAP] register to determine where we should boot.
206 * If we want to boot from the alternate boot bank, we need to tell the PIXIS
207 * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
209 static void read_from_px_regs_altbank(int set)
211 u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
214 tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
216 tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
218 out_8(pixis_base + PIXIS_VCFGEN1, tmp);
221 /* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
222 * tells the PIXIS what the alternate flash bank is.
224 * Note that it's not really a mask. It contains the actual LBMAP bits that
225 * must be set to select the alternate bank. This code assumes that the
226 * primary bank has these bits set to 0, and the alternate bank has these
229 #ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
230 #define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
233 /* Tell the PIXIS to boot from the default flash bank
235 * Program the default flash bank into the VBOOT register. This register is
236 * used only if PX_VCFGEN1[FLASH]=1.
238 static void clear_altbank(void)
240 clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
243 /* Tell the PIXIS to boot from the alternate flash bank
245 * Program the alternate flash bank into the VBOOT register. This register is
246 * used only if PX_VCFGEN1[FLASH]=1.
248 static void set_altbank(void)
250 setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
253 /* Reset the board with watchdog disabled.
255 * This respects the altbank setting.
257 static void set_px_go(void)
259 /* Disable the VELA sequencer and watchdog */
260 clrbits_8(pixis_base + PIXIS_VCTL, 9);
262 /* Reboot by starting the VELA sequencer */
263 setbits_8(pixis_base + PIXIS_VCTL, 0x1);
268 /* Reset the board with watchdog enabled.
270 * This respects the altbank setting.
272 static void set_px_go_with_watchdog(void)
274 /* Disable the VELA sequencer */
275 clrbits_8(pixis_base + PIXIS_VCTL, 1);
277 /* Enable the watchdog and reboot by starting the VELA sequencer */
278 setbits_8(pixis_base + PIXIS_VCTL, 0x9);
283 /* Disable the watchdog
286 static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
289 /* Disable the VELA sequencer and the watchdog */
290 clrbits_8(pixis_base + PIXIS_VCTL, 9);
296 diswd, 1, 0, pixis_disable_watchdog_cmd,
297 "Disable watchdog timer",
301 #ifdef CONFIG_PIXIS_SGMII_CMD
303 /* Enable or disable SGMII mode for a TSEC
305 static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
309 unsigned char switch_mask;
311 if ((argc > 2) && (strcmp(argv[1], "all") != 0))
312 which_tsec = simple_strtoul(argv[1], NULL, 0);
314 switch (which_tsec) {
317 mask = PIXIS_VSPEED2_TSEC1SER;
318 switch_mask = PIXIS_VCFGEN1_TSEC1SER;
323 mask = PIXIS_VSPEED2_TSEC2SER;
324 switch_mask = PIXIS_VCFGEN1_TSEC2SER;
329 mask = PIXIS_VSPEED2_TSEC3SER;
330 switch_mask = PIXIS_VCFGEN1_TSEC3SER;
335 mask = PIXIS_VSPEED2_TSEC4SER;
336 switch_mask = PIXIS_VCFGEN1_TSEC4SER;
340 mask = PIXIS_VSPEED2_MASK;
341 switch_mask = PIXIS_VCFGEN1_MASK;
345 /* Toggle whether the switches or FPGA control the settings */
346 if (!strcmp(argv[argc - 1], "switch"))
347 clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
349 setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
351 /* If it's not the switches, enable or disable SGMII, as specified */
352 if (!strcmp(argv[argc - 1], "on"))
353 clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
354 else if (!strcmp(argv[argc - 1], "off"))
355 setbits_8(pixis_base + PIXIS_VSPEED2, mask);
361 pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
363 " - Enable or disable SGMII mode for a given TSEC \n",
364 "\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
365 " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
366 " on - enables SGMII\n"
367 " off - disables SGMII\n"
368 " switch - use switch settings"
374 * This function takes the non-integral cpu:mpx pll ratio
375 * and converts it to an integer that can be used to assign
376 * FPGA register values.
377 * input: strptr i.e. argv[2]
379 static unsigned long strfractoint(char *strptr)
384 unsigned long intval = 0, decval = 0;
385 char intarr[3], decarr[3];
387 /* Assign the integer part to intarr[]
388 * If there is no decimal point i.e.
389 * if the ratio is an integral value
390 * simply create the intarr.
393 while (strptr[i] != '.') {
394 if (strptr[i] == 0) {
398 intarr[i] = strptr[i];
405 /* Currently needed only for single digit corepll ratios */
410 i++; /* Skipping the decimal point */
411 while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
412 decarr[j] = strptr[i];
420 for (i = 0; i < j; i++)
422 decval = simple_strtoul(decarr, NULL, 10);
425 intval = simple_strtoul(intarr, NULL, 10);
426 intval = intval * mulconst;
428 return intval + decval;
431 static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
435 char *p_cf_sysclk = NULL;
436 char *p_cf_corepll = NULL;
437 char *p_cf_mpxpll = NULL;
438 char *p_altbank = NULL;
440 int unknown_param = 0;
443 * No args is a simple reset request.
450 for (i = 1; i < argc; i++) {
451 if (strcmp(argv[i], "cf") == 0) {
456 p_cf_sysclk = argv[i+1];
457 p_cf_corepll = argv[i+2];
458 p_cf_mpxpll = argv[i+3];
463 if (strcmp(argv[i], "altbank") == 0) {
468 if (strcmp(argv[i], "wd") == 0) {
477 * Check that cf has all required parms
479 if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
481 #ifdef CONFIG_SYS_LONGHELP
488 * PIXIS seems to be sensitive to the ordering of
489 * the registers that are touched.
491 read_from_px_regs(0);
494 read_from_px_regs_altbank(0);
499 * Clock configuration specified.
502 unsigned long sysclk;
503 unsigned long corepll;
504 unsigned long mpxpll;
506 sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
507 corepll = strfractoint(p_cf_corepll);
508 mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
510 if (!(set_px_sysclk(sysclk)
511 && set_px_corepll(corepll)
512 && set_px_mpxpll(mpxpll))) {
513 #ifdef CONFIG_SYS_LONGHELP
518 read_from_px_regs(1);
524 * NOTE CHANGE IN BEHAVIOR: previous code would default
525 * to enabling watchdog if altbank is specified.
526 * Now the watchdog must be enabled explicitly using 'wd'.
530 read_from_px_regs_altbank(1);
534 * Reset with watchdog specified.
537 set_px_go_with_watchdog();
542 * Shouldn't be reached.
549 pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
550 "Reset the board using the FPGA sequencer",
552 " pixis_reset [altbank]\n"
553 " pixis_reset altbank wd\n"
554 " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
555 " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"