2 * Copyright 2006 Freescale Semiconductor
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/cache.h>
33 static ulong strfractoint(uchar *strptr);
39 void pixis_reset(void)
41 out8(PIXIS_BASE + PIXIS_RST, 0);
46 * Per table 27, page 58 of MPC8641HPCN spec.
48 int set_px_sysclk(ulong sysclk)
50 u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
102 printf("Unsupported SYSCLK frequency.\n");
106 vclkh = (sysclk_s << 5) | sysclk_r;
109 out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
110 out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
112 out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
118 int set_px_mpxpll(ulong mpxpll)
135 printf("Unsupported MPXPLL ratio.\n");
139 tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
140 tmp = (tmp & 0xF0) | (val & 0x0F);
141 out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
147 int set_px_corepll(ulong corepll)
152 switch ((int)corepll) {
172 printf("Unsupported COREPLL ratio.\n");
176 tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
177 tmp = (tmp & 0xE0) | (val & 0x1F);
178 out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
184 void read_from_px_regs(int set)
187 u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
193 out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
197 void read_from_px_regs_altbank(int set)
200 u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
206 out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
209 #ifndef CFG_PIXIS_VBOOT_MASK
210 #define CFG_PIXIS_VBOOT_MASK 0x40
213 void set_altbank(void)
217 tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
218 tmp ^= CFG_PIXIS_VBOOT_MASK;
220 out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
228 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
230 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
232 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
234 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
238 void set_px_go_with_watchdog(void)
242 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
244 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
246 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
248 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
252 int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
253 int flag, int argc, char *argv[])
257 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
259 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
261 /* setting VCTL[WDEN] to 0 to disable watch dog */
262 tmp = in8(PIXIS_BASE + PIXIS_VCTL);
264 out8(PIXIS_BASE + PIXIS_VCTL, tmp);
270 diswd, 1, 0, pixis_disable_watchdog_cmd,
271 "diswd - Disable watchdog timer \n",
275 * This function takes the non-integral cpu:mpx pll ratio
276 * and converts it to an integer that can be used to assign
277 * FPGA register values.
278 * input: strptr i.e. argv[2]
281 static ulong strfractoint(uchar *strptr)
285 int intarr_len = 0, decarr_len = 0, no_dec = 0;
286 ulong intval = 0, decval = 0;
287 uchar intarr[3], decarr[3];
289 /* Assign the integer part to intarr[]
290 * If there is no decimal point i.e.
291 * if the ratio is an integral value
292 * simply create the intarr.
295 while (strptr[i] != 46) {
296 if (strptr[i] == 0) {
300 intarr[i] = strptr[i];
304 /* Assign length of integer part to intarr_len. */
309 /* Currently needed only for single digit corepll ratios */
314 i++; /* Skipping the decimal point */
315 while ((strptr[i] > 47) && (strptr[i] < 58)) {
316 decarr[j] = strptr[i];
325 for (i = 0; i < decarr_len; i++)
327 decval = simple_strtoul((char *)decarr, NULL, 10);
330 intval = simple_strtoul((char *)intarr, NULL, 10);
331 intval = intval * mulconst;
333 retval = intval + decval;
340 pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
346 * No args is a simple reset request.
353 if (strcmp(argv[1], "cf") == 0) {
356 * Reset with frequency changed:
357 * cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
364 read_from_px_regs(0);
366 val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
368 corepll = strfractoint((uchar *)argv[3]);
369 val = val + set_px_corepll(corepll);
370 val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
372 puts("Setting registers VCFGEN0 and VCTL\n");
373 read_from_px_regs(1);
374 puts("Resetting board with values from ");
375 puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
382 while (1) ; /* Not reached */
384 } else if (strcmp(argv[1], "altbank") == 0) {
387 * Reset using alternate flash bank:
391 * Reset from alternate bank without changing
392 * frequency and without watchdog timer enabled.
395 read_from_px_regs(0);
396 read_from_px_regs_altbank(0);
401 puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
403 read_from_px_regs_altbank(1);
404 puts("Resetting board to boot from the other bank.\n");
407 } else if (strcmp(argv[2], "cf") == 0) {
409 * Reset with frequency changed
410 * altbank cf <SYSCLK freq> <COREPLL ratio>
413 read_from_px_regs(0);
414 read_from_px_regs_altbank(0);
415 val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
416 corepll = strfractoint((uchar *)argv[4]);
417 val = val + set_px_corepll(corepll);
418 val = val + set_px_mpxpll(simple_strtoul(argv[5],
421 puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
423 read_from_px_regs(1);
424 read_from_px_regs_altbank(1);
425 puts("Enabling watchdog timer on the FPGA\n");
426 puts("Resetting board with values from ");
427 puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
428 puts("to boot from the other bank.\n");
429 set_px_go_with_watchdog();
435 while (1) ; /* Not reached */
437 } else if (strcmp(argv[2], "wd") == 0) {
439 * Reset from alternate bank without changing
440 * frequencies but with watchdog timer enabled:
443 read_from_px_regs(0);
444 read_from_px_regs_altbank(0);
445 puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
447 read_from_px_regs_altbank(1);
448 puts("Enabling watchdog timer on the FPGA\n");
449 puts("Resetting board to boot from the other bank.\n");
450 set_px_go_with_watchdog();
451 while (1) ; /* Not reached */
468 pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
469 "pixis_reset - Reset the board using the FPGA sequencer\n",
471 " pixis_reset [altbank]\n"
472 " pixis_reset altbank wd\n"
473 " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
474 " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"