2 * Copyright 2011 Freescale Semiconductor
3 * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * This file provides support for the QIXIS of some Freescale reference boards.
13 #include <linux/time.h>
17 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
18 u8 qixis_read_i2c(unsigned int reg)
20 return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
23 void qixis_write_i2c(unsigned int reg, u8 value)
26 i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
31 u8 qixis_read(unsigned int reg)
33 void *p = (void *)QIXIS_BASE;
38 void qixis_write(unsigned int reg, u8 value)
40 void *p = (void *)QIXIS_BASE;
42 out_8(p + reg, value);
46 u16 qixis_read_minor(void)
50 /* this data is in little endian */
51 QIXIS_WRITE(tagdata, 5);
52 minor = QIXIS_READ(tagdata);
53 QIXIS_WRITE(tagdata, 6);
54 minor += QIXIS_READ(tagdata) << 8;
59 char *qixis_read_time(char *result)
64 /* timestamp is in 32-bit big endian */
65 for (i = 8; i <= 11; i++) {
66 QIXIS_WRITE(tagdata, i);
67 time = (time << 8) + QIXIS_READ(tagdata);
70 return ctime_r(&time, result);
73 char *qixis_read_tag(char *buf)
78 for (i = 16; i <= 63; i++) {
79 QIXIS_WRITE(tagdata, i);
80 tag = QIXIS_READ(tagdata);
92 * return the string of binary of u8 in the format of
93 * 1010 10_0. The masked bit is filled as underscore.
95 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
101 for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
102 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
104 for (i = 0x08; i > 0 ; i >>= 1, ptr++)
105 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
112 #ifdef QIXIS_RST_FORCE_MEM
113 void board_assert_mem_reset(void)
117 rst = QIXIS_READ(rst_frc[0]);
118 if (!(rst & QIXIS_RST_FORCE_MEM))
119 QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
122 void board_deassert_mem_reset(void)
126 rst = QIXIS_READ(rst_frc[0]);
127 if (rst & QIXIS_RST_FORCE_MEM)
128 QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
132 void qixis_reset(void)
134 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
137 void qixis_bank_reset(void)
139 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
140 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
143 static void __maybe_unused set_lbmap(int lbmap)
147 reg = QIXIS_READ(brdcfg[0]);
148 reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
149 QIXIS_WRITE(brdcfg[0], reg);
152 static void __maybe_unused set_rcw_src(int rcw_src)
156 reg = QIXIS_READ(dutcfg[1]);
157 reg = (reg & ~1) | (rcw_src & 1);
158 QIXIS_WRITE(dutcfg[1], reg);
159 QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
162 static void qixis_dump_regs(void)
166 printf("id = %02x\n", QIXIS_READ(id));
167 printf("arch = %02x\n", QIXIS_READ(arch));
168 printf("scver = %02x\n", QIXIS_READ(scver));
169 printf("model = %02x\n", QIXIS_READ(model));
170 printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
171 printf("aux = %02x\n", QIXIS_READ(aux));
172 for (i = 0; i < 16; i++)
173 printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
174 for (i = 0; i < 16; i++)
175 printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
176 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
177 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
178 printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
179 QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
180 printf("aux = %02x\n", QIXIS_READ(aux));
181 printf("watch = %02x\n", QIXIS_READ(watch));
182 printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
183 printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
184 printf("present = %02x\n", QIXIS_READ(present));
185 printf("present2 = %02x\n", QIXIS_READ(present2));
186 printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
187 printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
188 printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
189 printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
192 static void __qixis_dump_switch(void)
194 puts("Reverse engineering switch is not implemented for this board\n");
197 void qixis_dump_switch(void)
198 __attribute__((weak, alias("__qixis_dump_switch")));
200 int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
205 set_lbmap(QIXIS_LBMAP_DFLTBANK);
207 } else if (strcmp(argv[1], "altbank") == 0) {
208 set_lbmap(QIXIS_LBMAP_ALTBANK);
210 } else if (strcmp(argv[1], "nand") == 0) {
211 #ifdef QIXIS_LBMAP_NAND
212 QIXIS_WRITE(rst_ctl, 0x30);
213 QIXIS_WRITE(rcfg_ctl, 0);
214 set_lbmap(QIXIS_LBMAP_NAND);
215 set_rcw_src(QIXIS_RCW_SRC_NAND);
216 QIXIS_WRITE(rcfg_ctl, 0x20);
217 QIXIS_WRITE(rcfg_ctl, 0x21);
219 printf("Not implemented\n");
221 } else if (strcmp(argv[1], "sd") == 0) {
222 #ifdef QIXIS_LBMAP_SD
223 QIXIS_WRITE(rst_ctl, 0x30);
224 QIXIS_WRITE(rcfg_ctl, 0);
225 set_lbmap(QIXIS_LBMAP_SD);
226 set_rcw_src(QIXIS_RCW_SRC_SD);
227 QIXIS_WRITE(rcfg_ctl, 0x20);
228 QIXIS_WRITE(rcfg_ctl, 0x21);
230 printf("Not implemented\n");
232 } else if (strcmp(argv[1], "sd_qspi") == 0) {
233 #ifdef QIXIS_LBMAP_SD_QSPI
234 QIXIS_WRITE(rst_ctl, 0x30);
235 QIXIS_WRITE(rcfg_ctl, 0);
236 set_lbmap(QIXIS_LBMAP_SD_QSPI);
237 set_rcw_src(QIXIS_RCW_SRC_SD);
238 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
239 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
241 printf("Not implemented\n");
243 } else if (strcmp(argv[1], "qspi") == 0) {
244 #ifdef QIXIS_LBMAP_QSPI
245 QIXIS_WRITE(rst_ctl, 0x30);
246 QIXIS_WRITE(rcfg_ctl, 0);
247 set_lbmap(QIXIS_LBMAP_QSPI);
248 set_rcw_src(QIXIS_RCW_SRC_QSPI);
249 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
250 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
252 printf("Not implemented\n");
254 } else if (strcmp(argv[1], "watchdog") == 0) {
255 static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
256 "1min", "2min", "4min", "8min"};
257 u8 rcfg = QIXIS_READ(rcfg_ctl);
259 if (argv[2] == NULL) {
260 printf("qixis watchdog <watchdog_period>\n");
263 for (i = 0; i < ARRAY_SIZE(period); i++) {
264 if (strcmp(argv[2], period[i]) == 0) {
265 /* disable watchdog */
266 QIXIS_WRITE(rcfg_ctl,
267 rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
268 QIXIS_WRITE(watch, ((i<<2) - 1));
269 QIXIS_WRITE(rcfg_ctl, rcfg);
273 } else if (strcmp(argv[1], "dump") == 0) {
276 } else if (strcmp(argv[1], "switch") == 0) {
280 printf("Invalid option: %s\n", argv[1]);
288 qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
289 "Reset the board using the FPGA sequencer",
290 "- hard reset to default bank\n"
291 "qixis_reset altbank - reset to alternate bank\n"
292 "qixis_reset nand - reset to nand\n"
293 "qixis_reset sd - reset to sd\n"
294 "qixis_reset sd_qspi - reset to sd with qspi support\n"
295 "qixis_reset qspi - reset to qspi\n"
296 "qixis watchdog <watchdog_period> - set the watchdog period\n"
297 " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
298 "qixis_reset dump - display the QIXIS registers\n"
299 "qixis_reset switch - display switch\n"