2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/compiler.h>
12 #include <asm/processor.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
21 #include "../common/ngpixis.h"
22 #include "corenet_ds.h"
24 DECLARE_GLOBAL_DATA_PTR;
29 struct cpu_type *cpu = gd->arch.cpu;
30 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
32 static const char * const freq[] = {"100", "125", "156.25", "212.5" };
34 printf("Board: %sDS, ", cpu->name);
35 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
36 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
38 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
39 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
42 printf("vBank: %d\n", sw);
48 printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
50 /* Display the RCW, so that no one gets confused as to what RCW
51 * we're actually using for this boot.
53 puts("Reset Configuration Word (RCW):");
54 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
55 u32 rcw = in_be32(&gur->rcwsr[i]);
58 printf("\n %08x:", i * 4);
63 /* Display the actual SERDES reference clocks as configured by the
64 * dip switches on the board. Note that the SWx registers could
65 * technically be set to force the reference clocks to match the
66 * values that the SERDES expects (or vice versa). For now, however,
67 * we just display both values and hope the user notices when they
70 puts("SERDES Reference Clocks: ");
71 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
72 || defined(CONFIG_P5040DS)
73 sw = in_8(&PIXIS_SW(5));
74 for (i = 0; i < 3; i++) {
75 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
77 printf("Bank%u=%sMhz ", i+1, freq[clock]);
80 /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
81 sw = in_8(&PIXIS_SW(9));
82 printf("Bank4=%sMhz ", freq[sw & 3]);
86 sw = in_8(&PIXIS_SW(3));
87 /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
88 /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
89 /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
90 printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
91 printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
92 printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
98 int board_early_init_f(void)
100 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
103 * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
104 * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
105 * the noise introduced by these unterminated and unused clock pairs.
107 setbits_be32(&gur->ddrclkdr, 0x001B001B);
112 int board_early_init_r(void)
114 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
115 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
118 * Remap Boot flash + PROMJET region to caching-inhibited
119 * so that flash can be erased properly.
122 /* Flush d-cache and invalidate i-cache of any FLASH data */
126 /* invalidate existing TLB entry for flash + promjet */
127 disable_tlb(flash_esel);
129 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
130 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
131 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
134 #ifdef CONFIG_SYS_DPAA_QBMAN
141 static const char *serdes_clock_to_string(u32 clock)
144 case SRDS_PLLCR0_RFCK_SEL_100:
146 case SRDS_PLLCR0_RFCK_SEL_125:
148 case SRDS_PLLCR0_RFCK_SEL_156_25:
155 #define NUM_SRDS_BANKS 3
157 int misc_init_r(void)
159 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
160 u32 actual[NUM_SRDS_BANKS];
164 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
165 || defined(CONFIG_P5040DS)
166 sw = in_8(&PIXIS_SW(5));
167 for (i = 0; i < 3; i++) {
168 unsigned int clock = (sw >> (6 - (2 * i))) & 3;
171 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
174 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
177 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
180 printf("Warning: SDREFCLK%u switch setting of '11' is "
181 "unsupported\n", i + 1);
186 /* Warn if the expected SERDES reference clocks don't match the
187 * actual reference clocks. This needs to be done after calling
188 * p4080_erratum_serdes8(), since that function may modify the clocks.
190 sw = in_8(&PIXIS_SW(3));
191 actual[0] = (sw & 0x40) ?
192 SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
193 actual[1] = (sw & 0x20) ?
194 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
195 actual[2] = (sw & 0x10) ?
196 SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
199 for (i = 0; i < NUM_SRDS_BANKS; i++) {
200 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
201 if (expected != actual[i]) {
202 printf("Warning: SERDES bank %u expects reference clock"
203 " %sMHz, but actual is %sMHz\n", i + 1,
204 serdes_clock_to_string(expected),
205 serdes_clock_to_string(actual[i]));
212 void ft_board_setup(void *blob, bd_t *bd)
217 ft_cpu_setup(blob, bd);
219 base = getenv_bootm_low();
220 size = getenv_bootm_size();
222 fdt_fixup_memory(blob, (u64)base, (u64)size);
225 pci_of_setup(blob, bd);
228 fdt_fixup_liodn(blob);
229 fdt_fixup_dr_usb(blob, bd);
231 #ifdef CONFIG_SYS_DPAA_FMAN
232 fdt_fixup_fman_ethernet(blob);
233 fdt_fixup_board_enet(blob);