2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
13 #include <asm/fsl_ddr_sdram.h>
14 #include <asm/fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
17 DECLARE_GLOBAL_DATA_PTR;
21 * Fixed sdram init -- doesn't use serial presence detect.
23 extern fixed_ddr_parm_t fixed_ddr_parm_0[];
24 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
25 extern fixed_ddr_parm_t fixed_ddr_parm_1[];
28 phys_size_t fixed_sdram(void)
32 fsl_ddr_cfg_regs_t ddr_cfg_regs;
34 unsigned int lawbar1_target_id;
35 ulong ddr_freq, ddr_freq_mhz;
37 ddr_freq = get_ddr_freq(0);
38 ddr_freq_mhz = ddr_freq / 1000000;
40 printf("Configuring DDR for %s MT/s data rate\n",
41 strmhz(buf, ddr_freq));
43 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
44 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
45 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
47 fixed_ddr_parm_0[i].ddr_settings,
48 sizeof(ddr_cfg_regs));
53 if (fixed_ddr_parm_0[i].max_freq == 0)
54 panic("Unsupported DDR data rate %s MT/s data rate\n",
55 strmhz(buf, ddr_freq));
57 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
58 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
59 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
61 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
63 fixed_ddr_parm_1[i].ddr_settings,
64 sizeof(ddr_cfg_regs));
65 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
66 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
70 * setup laws for DDR. If not interleaving, presuming half memory on
71 * DDR1 and the other half on DDR2
73 if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
74 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
76 LAW_TRGT_IF_DDR_INTRLV) < 0) {
77 printf("ERROR setting Local Access Windows for DDR\n");
81 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
82 /* We require both controllers have identical DIMMs */
83 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
84 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
86 lawbar1_target_id) < 0) {
87 printf("ERROR setting Local Access Windows for DDR\n");
90 lawbar1_target_id = LAW_TRGT_IF_DDR_2;
91 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
93 lawbar1_target_id) < 0) {
94 printf("ERROR setting Local Access Windows for DDR\n");
98 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
99 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
101 lawbar1_target_id) < 0) {
102 printf("ERROR setting Local Access Windows for DDR\n");
111 u32 datarate_mhz_low;
112 u32 datarate_mhz_high;
117 u32 write_data_delay;
119 } board_specific_parameters_t;
121 /* ranges for parameters:
122 * wr_data_delay = 0-6
128 /* XXX: these values need to be checked for all interleaving modes. */
129 /* XXX: No reliable dual-rank 800 MHz setting has been found. It may
130 * seem reliable, but errors will appear when memory intensive
132 /* XXX: Single rank at 800 MHz is OK. */
133 const board_specific_parameters_t board_specific_parameters[][30] = {
136 * memory controller 0
137 * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
138 * mhz| mhz|ranks|adjst| start | delay|
140 { 0, 850, 4, 4, 6, 0xff, 2, 0},
141 {851, 950, 4, 5, 7, 0xff, 2, 0},
142 {951, 1050, 4, 5, 8, 0xff, 2, 0},
143 {1051, 1250, 4, 5, 10, 0xff, 2, 0},
144 {1251, 1350, 4, 5, 11, 0xff, 2, 0},
145 { 0, 850, 2, 5, 6, 0xff, 2, 0},
146 {851, 950, 2, 5, 7, 0xff, 2, 0},
147 {951, 1050, 2, 5, 7, 0xff, 2, 0},
148 {1051, 1250, 2, 4, 6, 0xff, 2, 0},
149 {1251, 1350, 2, 5, 7, 0xff, 2, 0},
154 * memory controller 1
155 * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
156 * mhz| mhz|ranks|adjst| start | delay|
158 { 0, 850, 4, 4, 6, 0xff, 2, 0},
159 {851, 950, 4, 5, 7, 0xff, 2, 0},
160 {951, 1050, 4, 5, 8, 0xff, 2, 0},
161 {1051, 1250, 4, 5, 10, 0xff, 2, 0},
162 {1251, 1350, 4, 5, 11, 0xff, 2, 0},
163 { 0, 850, 2, 5, 6, 0xff, 2, 0},
164 {851, 950, 2, 5, 7, 0xff, 2, 0},
165 {951, 1050, 2, 5, 7, 0xff, 2, 0},
166 {1051, 1250, 2, 4, 6, 0xff, 2, 0},
167 {1251, 1350, 2, 5, 7, 0xff, 2, 0},
171 void fsl_ddr_board_options(memctl_options_t *popts,
172 dimm_params_t *pdimm,
173 unsigned int ctrl_num)
175 const board_specific_parameters_t *pbsp =
176 &(board_specific_parameters[ctrl_num][0]);
177 u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
178 sizeof(board_specific_parameters[0][0]);
182 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
183 * freqency and n_banks specified in board_specific_parameters table.
185 ddr_freq = get_ddr_freq(0) / 1000000;
186 for (i = 0; i < num_params; i++) {
187 if (ddr_freq >= pbsp->datarate_mhz_low &&
188 ddr_freq <= pbsp->datarate_mhz_high &&
189 pdimm[0].n_ranks == pbsp->n_ranks) {
190 popts->cpo_override = pbsp->cpo;
191 popts->write_data_delay = pbsp->write_data_delay;
192 popts->clk_adjust = pbsp->clk_adjust;
193 popts->wrlvl_start = pbsp->wrlvl_start;
194 popts->twoT_en = pbsp->force_2T;
200 if (i == num_params) {
201 printf("Warning: board specific timing not found "
202 "for data rate %lu MT/s!\n", ddr_freq);
206 * Factors to consider for half-strength driver enable:
207 * - number of DIMMs installed
209 popts->half_strength_driver_enable = 0;
211 * Write leveling override
213 popts->wrlvl_override = 1;
214 popts->wrlvl_sample = 0xf;
217 * Rtt and Rtt_WR override
219 popts->rtt_override = 0;
221 /* Enable ZQ calibration */
224 /* DHC_EN =1, ODT = 60 Ohm */
225 popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
227 /* override SPD values. rcw_2 should vary at differnt speed */
228 if (pdimm[0].registered_dimm == 1) {
229 popts->rcw_override = 1;
230 popts->rcw_1 = 0x000a5a00;
232 popts->rcw_2 = 0x00000000;
233 else if (ddr_freq <= 1066)
234 popts->rcw_2 = 0x00100000;
235 else if (ddr_freq <= 1333)
236 popts->rcw_2 = 0x00200000;
238 popts->rcw_2 = 0x00300000;
242 phys_size_t initdram(int board_type)
244 phys_size_t dram_size;
246 puts("Initializing....");
250 dram_size = fsl_ddr_sdram();
252 puts("using fixed parameters\n");
253 dram_size = fixed_sdram();
256 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
257 dram_size *= 0x100000;