git.sur5r.net Git - u-boot/blob - board/freescale/corenet_ds/ddr.c

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <i2c.h>
  11 #include <hwconfig.h>
  12 #include <asm/mmu.h>
  13 #include <asm/fsl_ddr_sdram.h>
  14 #include <asm/fsl_ddr_dimm_params.h>
  15 #include <asm/fsl_law.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  20                                    unsigned int ctrl_num);
  21
  22
  23 /*
  24  * Fixed sdram init -- doesn't use serial presence detect.
  25  */
  26 extern fixed_ddr_parm_t fixed_ddr_parm_0[];
  27 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
  28 extern fixed_ddr_parm_t fixed_ddr_parm_1[];
  29 #endif
  30
  31 phys_size_t fixed_sdram(void)
  32 {
  33         int i;
  34         char buf[32];
  35         fsl_ddr_cfg_regs_t ddr_cfg_regs;
  36         phys_size_t ddr_size;
  37         unsigned int lawbar1_target_id;
  38         ulong ddr_freq, ddr_freq_mhz;
  39
  40         ddr_freq = get_ddr_freq(0);
  41         ddr_freq_mhz = ddr_freq / 1000000;
  42
  43         printf("Configuring DDR for %s MT/s data rate\n",
  44                                 strmhz(buf, ddr_freq));
  45
  46         for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
  47                 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
  48                    (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
  49                         memcpy(&ddr_cfg_regs,
  50                                 fixed_ddr_parm_0[i].ddr_settings,
  51                                 sizeof(ddr_cfg_regs));
  52                         break;
  53                 }
  54         }
  55
  56         if (fixed_ddr_parm_0[i].max_freq == 0)
  57                 panic("Unsupported DDR data rate %s MT/s data rate\n",
  58                         strmhz(buf, ddr_freq));
  59
  60         ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  61         ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
  62         fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
  63
  64 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
  65         memcpy(&ddr_cfg_regs,
  66                 fixed_ddr_parm_1[i].ddr_settings,
  67                 sizeof(ddr_cfg_regs));
  68         ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
  69         fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
  70 #endif
  71
  72         /*
  73          * setup laws for DDR. If not interleaving, presuming half memory on
  74          * DDR1 and the other half on DDR2
  75          */
  76         if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
  77                 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  78                                  ddr_size,
  79                                  LAW_TRGT_IF_DDR_INTRLV) < 0) {
  80                         printf("ERROR setting Local Access Windows for DDR\n");
  81                         return 0;
  82                 }
  83         } else {
  84 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
  85                 /* We require both controllers have identical DIMMs */
  86                 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
  87                 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  88                                  ddr_size / 2,
  89                                  lawbar1_target_id) < 0) {
  90                         printf("ERROR setting Local Access Windows for DDR\n");
  91                         return 0;
  92                 }
  93                 lawbar1_target_id = LAW_TRGT_IF_DDR_2;
  94                 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
  95                                  ddr_size / 2,
  96                                  lawbar1_target_id) < 0) {
  97                         printf("ERROR setting Local Access Windows for DDR\n");
  98                         return 0;
  99                 }
 100 #else
 101                 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
 102                 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
 103                                  ddr_size,
 104                                  lawbar1_target_id) < 0) {
 105                         printf("ERROR setting Local Access Windows for DDR\n");
 106                         return 0;
 107                 }
 108 #endif
 109         }
 110         return ddr_size;
 111 }
 112
 113 static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
 114 {
 115         int ret;
 116
 117         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
 118         if (ret) {
 119                 debug("DDR: failed to read SPD from address %u\n", i2c_address);
 120                 memset(spd, 0, sizeof(ddr3_spd_eeprom_t));
 121         }
 122 }
 123
 124 unsigned int fsl_ddr_get_mem_data_rate(void)
 125 {
 126         return get_ddr_freq(0);
 127 }
 128
 129 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
 130                       unsigned int ctrl_num)
 131 {
 132         unsigned int i;
 133         unsigned int i2c_address = 0;
 134
 135         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
 136                 if (ctrl_num == 0 && i == 0)
 137                         i2c_address = SPD_EEPROM_ADDRESS1;
 138                 else if (ctrl_num == 1 && i == 0)
 139                         i2c_address = SPD_EEPROM_ADDRESS2;
 140
 141                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 142         }
 143 }
 144
 145 typedef struct {
 146         u32 datarate_mhz_low;
 147         u32 datarate_mhz_high;
 148         u32 n_ranks;
 149         u32 clk_adjust;
 150         u32 wrlvl_start;
 151         u32 cpo;
 152         u32 write_data_delay;
 153         u32 force_2T;
 154 } board_specific_parameters_t;
 155
 156 /* ranges for parameters:
 157  *  wr_data_delay = 0-6
 158  *  clk adjust = 0-8
 159  *  cpo 2-0x1E (30)
 160  */
 161
 162
 163 /* XXX: these values need to be checked for all interleaving modes.  */
 164 /* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
 165  *      seem reliable, but errors will appear when memory intensive
 166  *      program is run. */
 167 /* XXX: Single rank at 800 MHz is OK.  */
 168 const board_specific_parameters_t board_specific_parameters[][30] = {
 169         {
 170         /*
 171          * memory controller 0
 172          *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
 173          * mhz| mhz|ranks|adjst| start | delay|
 174          */
 175                 {  0, 850,    4,    4,     6,   0xff,    2,  0},
 176                 {851, 950,    4,    5,     7,   0xff,    2,  0},
 177                 {951, 1050,   4,    5,     8,   0xff,    2,  0},
 178                 {1051, 1250,  4,    5,    10,   0xff,    2,  0},
 179                 {1251, 1350,  4,    5,    11,   0xff,    2,  0},
 180                 {  0, 850,    2,    5,     6,   0xff,    2,  0},
 181                 {851, 950,    2,    5,     7,   0xff,    2,  0},
 182                 {951, 1050,   2,    5,     7,   0xff,    2,  0},
 183                 {1051, 1250,  2,    4,     6,   0xff,    2,  0},
 184                 {1251, 1350,  2,    5,     7,   0xff,    2,  0},
 185         },
 186
 187         {
 188         /*
 189          * memory controller 1
 190          *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
 191          * mhz| mhz|ranks|adjst| start | delay|
 192          */
 193                 {  0, 850,    4,    4,     6,   0xff,    2,  0},
 194                 {851, 950,    4,    5,     7,   0xff,    2,  0},
 195                 {951, 1050,   4,    5,     8,   0xff,    2,  0},
 196                 {1051, 1250,  4,    5,    10,   0xff,    2,  0},
 197                 {1251, 1350,  4,    5,    11,   0xff,    2,  0},
 198                 {  0, 850,    2,    5,     6,   0xff,    2,  0},
 199                 {851, 950,    2,    5,     7,   0xff,    2,  0},
 200                 {951, 1050,   2,    5,     7,   0xff,    2,  0},
 201                 {1051, 1250,  2,    4,     6,   0xff,    2,  0},
 202                 {1251, 1350,  2,    5,     7,   0xff,    2,  0},
 203         }
 204 };
 205
 206 void fsl_ddr_board_options(memctl_options_t *popts,
 207                                 dimm_params_t *pdimm,
 208                                 unsigned int ctrl_num)
 209 {
 210         const board_specific_parameters_t *pbsp =
 211                                 &(board_specific_parameters[ctrl_num][0]);
 212         u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
 213                                 sizeof(board_specific_parameters[0][0]);
 214         u32 i;
 215         ulong ddr_freq;
 216
 217         /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
 218          * freqency and n_banks specified in board_specific_parameters table.
 219          */
 220         ddr_freq = get_ddr_freq(0) / 1000000;
 221         for (i = 0; i < num_params; i++) {
 222                 if (ddr_freq >= pbsp->datarate_mhz_low &&
 223                         ddr_freq <= pbsp->datarate_mhz_high &&
 224                         pdimm[0].n_ranks == pbsp->n_ranks) {
 225                         popts->cpo_override = pbsp->cpo;
 226                         popts->write_data_delay = pbsp->write_data_delay;
 227                         popts->clk_adjust = pbsp->clk_adjust;
 228                         popts->wrlvl_start = pbsp->wrlvl_start;
 229                         popts->twoT_en = pbsp->force_2T;
 230                 }
 231                 pbsp++;
 232         }
 233
 234         /*
 235          * Factors to consider for half-strength driver enable:
 236          *      - number of DIMMs installed
 237          */
 238         popts->half_strength_driver_enable = 0;
 239         /*
 240          * Write leveling override
 241          */
 242         popts->wrlvl_override = 1;
 243         popts->wrlvl_sample = 0xf;
 244
 245         /*
 246          * Rtt and Rtt_WR override
 247          */
 248         popts->rtt_override = 0;
 249
 250         /* Enable ZQ calibration */
 251         popts->zq_en = 1;
 252
 253         /* DHC_EN =1, ODT = 60 Ohm */
 254         popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 255
 256         /* override SPD values. rcw_2 should vary at differnt speed */
 257         if (pdimm[0].n_ranks == 4) {
 258                 popts->rcw_override = 1;
 259                 popts->rcw_1 = 0x000a5a00;
 260                 if (ddr_freq <= 800)
 261                         popts->rcw_2 = 0x00000000;
 262                 else if (ddr_freq <= 1066)
 263                         popts->rcw_2 = 0x00100000;
 264                 else if (ddr_freq <= 1333)
 265                         popts->rcw_2 = 0x00200000;
 266                 else
 267                         popts->rcw_2 = 0x00300000;
 268         }
 269 }
 270
 271 phys_size_t initdram(int board_type)
 272 {
 273         phys_size_t dram_size;
 274
 275         puts("Initializing....");
 276
 277         if (fsl_use_spd()) {
 278                 puts("using SPD\n");
 279                 dram_size = fsl_ddr_sdram();
 280         } else {
 281                 puts("using fixed parameters\n");
 282                 dram_size = fixed_sdram();
 283         }
 284
 285         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 286         dram_size *= 0x100000;
 287
 288         puts("    DDR: ");
 289         return dram_size;
 290 }