2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
13 #include <asm/fsl_ddr_sdram.h>
14 #include <asm/fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
17 DECLARE_GLOBAL_DATA_PTR;
21 * Fixed sdram init -- doesn't use serial presence detect.
23 extern fixed_ddr_parm_t fixed_ddr_parm_0[];
24 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
25 extern fixed_ddr_parm_t fixed_ddr_parm_1[];
28 phys_size_t fixed_sdram(void)
32 fsl_ddr_cfg_regs_t ddr_cfg_regs;
34 unsigned int lawbar1_target_id;
35 ulong ddr_freq, ddr_freq_mhz;
37 ddr_freq = get_ddr_freq(0);
38 ddr_freq_mhz = ddr_freq / 1000000;
40 printf("Configuring DDR for %s MT/s data rate\n",
41 strmhz(buf, ddr_freq));
43 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
44 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
45 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
47 fixed_ddr_parm_0[i].ddr_settings,
48 sizeof(ddr_cfg_regs));
53 if (fixed_ddr_parm_0[i].max_freq == 0)
54 panic("Unsupported DDR data rate %s MT/s data rate\n",
55 strmhz(buf, ddr_freq));
57 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
58 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
59 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
61 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
63 fixed_ddr_parm_1[i].ddr_settings,
64 sizeof(ddr_cfg_regs));
65 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
66 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
70 * setup laws for DDR. If not interleaving, presuming half memory on
71 * DDR1 and the other half on DDR2
73 if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
74 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
76 LAW_TRGT_IF_DDR_INTRLV) < 0) {
77 printf("ERROR setting Local Access Windows for DDR\n");
81 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
82 /* We require both controllers have identical DIMMs */
83 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
84 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
86 lawbar1_target_id) < 0) {
87 printf("ERROR setting Local Access Windows for DDR\n");
90 lawbar1_target_id = LAW_TRGT_IF_DDR_2;
91 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
93 lawbar1_target_id) < 0) {
94 printf("ERROR setting Local Access Windows for DDR\n");
98 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
99 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
101 lawbar1_target_id) < 0) {
102 printf("ERROR setting Local Access Windows for DDR\n");
110 static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
114 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
116 debug("DDR: failed to read SPD from address %u\n", i2c_address);
117 memset(spd, 0, sizeof(ddr3_spd_eeprom_t));
121 unsigned int fsl_ddr_get_mem_data_rate(void)
123 return get_ddr_freq(0);
126 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
127 unsigned int ctrl_num)
130 unsigned int i2c_address = 0;
132 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
133 if (ctrl_num == 0 && i == 0)
134 i2c_address = SPD_EEPROM_ADDRESS1;
135 else if (ctrl_num == 1 && i == 0)
136 i2c_address = SPD_EEPROM_ADDRESS2;
138 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
143 u32 datarate_mhz_low;
144 u32 datarate_mhz_high;
149 u32 write_data_delay;
151 } board_specific_parameters_t;
153 /* ranges for parameters:
154 * wr_data_delay = 0-6
160 /* XXX: these values need to be checked for all interleaving modes. */
161 /* XXX: No reliable dual-rank 800 MHz setting has been found. It may
162 * seem reliable, but errors will appear when memory intensive
164 /* XXX: Single rank at 800 MHz is OK. */
165 const board_specific_parameters_t board_specific_parameters[][30] = {
168 * memory controller 0
169 * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
170 * mhz| mhz|ranks|adjst| start | delay|
172 { 0, 850, 4, 4, 6, 0xff, 2, 0},
173 {851, 950, 4, 5, 7, 0xff, 2, 0},
174 {951, 1050, 4, 5, 8, 0xff, 2, 0},
175 {1051, 1250, 4, 5, 10, 0xff, 2, 0},
176 {1251, 1350, 4, 5, 11, 0xff, 2, 0},
177 { 0, 850, 2, 5, 6, 0xff, 2, 0},
178 {851, 950, 2, 5, 7, 0xff, 2, 0},
179 {951, 1050, 2, 5, 7, 0xff, 2, 0},
180 {1051, 1250, 2, 4, 6, 0xff, 2, 0},
181 {1251, 1350, 2, 5, 7, 0xff, 2, 0},
186 * memory controller 1
187 * lo| hi| num| clk| wrlvl | cpo |wrdata|2T
188 * mhz| mhz|ranks|adjst| start | delay|
190 { 0, 850, 4, 4, 6, 0xff, 2, 0},
191 {851, 950, 4, 5, 7, 0xff, 2, 0},
192 {951, 1050, 4, 5, 8, 0xff, 2, 0},
193 {1051, 1250, 4, 5, 10, 0xff, 2, 0},
194 {1251, 1350, 4, 5, 11, 0xff, 2, 0},
195 { 0, 850, 2, 5, 6, 0xff, 2, 0},
196 {851, 950, 2, 5, 7, 0xff, 2, 0},
197 {951, 1050, 2, 5, 7, 0xff, 2, 0},
198 {1051, 1250, 2, 4, 6, 0xff, 2, 0},
199 {1251, 1350, 2, 5, 7, 0xff, 2, 0},
203 void fsl_ddr_board_options(memctl_options_t *popts,
204 dimm_params_t *pdimm,
205 unsigned int ctrl_num)
207 const board_specific_parameters_t *pbsp =
208 &(board_specific_parameters[ctrl_num][0]);
209 u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
210 sizeof(board_specific_parameters[0][0]);
214 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
215 * freqency and n_banks specified in board_specific_parameters table.
217 ddr_freq = get_ddr_freq(0) / 1000000;
218 for (i = 0; i < num_params; i++) {
219 if (ddr_freq >= pbsp->datarate_mhz_low &&
220 ddr_freq <= pbsp->datarate_mhz_high &&
221 pdimm[0].n_ranks == pbsp->n_ranks) {
222 popts->cpo_override = pbsp->cpo;
223 popts->write_data_delay = pbsp->write_data_delay;
224 popts->clk_adjust = pbsp->clk_adjust;
225 popts->wrlvl_start = pbsp->wrlvl_start;
226 popts->twoT_en = pbsp->force_2T;
232 * Factors to consider for half-strength driver enable:
233 * - number of DIMMs installed
235 popts->half_strength_driver_enable = 0;
237 * Write leveling override
239 popts->wrlvl_override = 1;
240 popts->wrlvl_sample = 0xf;
243 * Rtt and Rtt_WR override
245 popts->rtt_override = 0;
247 /* Enable ZQ calibration */
250 /* DHC_EN =1, ODT = 60 Ohm */
251 popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
253 /* override SPD values. rcw_2 should vary at differnt speed */
254 if (pdimm[0].n_ranks == 4) {
255 popts->rcw_override = 1;
256 popts->rcw_1 = 0x000a5a00;
258 popts->rcw_2 = 0x00000000;
259 else if (ddr_freq <= 1066)
260 popts->rcw_2 = 0x00100000;
261 else if (ddr_freq <= 1333)
262 popts->rcw_2 = 0x00200000;
264 popts->rcw_2 = 0x00300000;
268 phys_size_t initdram(int board_type)
270 phys_size_t dram_size;
272 puts("Initializing....");
276 dram_size = fsl_ddr_sdram();
278 puts("using fixed parameters\n");
279 dram_size = fixed_sdram();
282 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
283 dram_size *= 0x100000;