2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
3 * Author: Timur Tabi <timur@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file handles the board muxing between the Fman Ethernet MACs and
10 * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
11 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
12 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
13 * XGMII PHY is provided via the XAUI riser card. Since there is only one
14 * Fman device on a P3041 and P5020, we only support one SGMII card and one
17 * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
18 * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
19 * always the same (0). The value for SGMII depends on which slot the riser is
20 * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
21 * the value is based on which slot the XAUI is inserted in.
23 * The SERDES configuration is used to determine where the SGMII and XAUI cards
24 * exist, and also which Fman MACs are routed to which PHYs. So for a given
25 * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
26 * to PHYs dynamically.
29 * This file also updates the device tree in three ways:
31 * 1) The status of each virtual MDIO node that is referenced by an Ethernet
32 * node is set to "okay".
34 * 2) The phy-handle property of each active Ethernet MAC node is set to the
35 * appropriate PHY node.
37 * 3) The "mux value" for each virtual MDIO node is set to the correct value,
38 * if necessary. Some virtual MDIO nodes do not have configurable mux
39 * values, so those values are hard-coded in the DTS. On the HYDRA board,
40 * the virtual MDIO node for the SGMII card needs to be updated.
42 * For all this to work, the device tree needs to have the following:
44 * 1) An alias for each PHY node that an Ethernet node could be routed to.
46 * 2) An alias for each real and virtual MDIO node that is disabled by default
47 * and might need to be enabled, and also might need to have its mux-value
53 #include <asm/fsl_serdes.h>
57 #include <fdt_support.h>
58 #include <asm/fsl_dtsec.h>
60 #include "../common/ngpixis.h"
61 #include "../common/fman.h"
63 #ifdef CONFIG_FMAN_ENET
65 #define BRDCFG1_EMI1_SEL_MASK 0x78
66 #define BRDCFG1_EMI1_SEL_SLOT1 0x10
67 #define BRDCFG1_EMI1_SEL_SLOT2 0x20
68 #define BRDCFG1_EMI1_SEL_SLOT5 0x30
69 #define BRDCFG1_EMI1_SEL_SLOT6 0x40
70 #define BRDCFG1_EMI1_SEL_SLOT7 0x50
71 #define BRDCFG1_EMI1_SEL_RGMII 0x00
72 #define BRDCFG1_EMI1_EN 0x08
73 #define BRDCFG1_EMI2_SEL_MASK 0x06
74 #define BRDCFG1_EMI2_SEL_SLOT1 0x00
75 #define BRDCFG1_EMI2_SEL_SLOT2 0x02
77 #define BRDCFG2_REG_GPIO_SEL 0x20
79 #define PHY_BASE_ADDR 0x00
82 * BRDCFG1 mask and value for each MAC
84 * This array contains the BRDCFG1 values (in mask/val format) that route the
85 * MDIO bus to a particular RGMII or SGMII PHY.
90 } mdio_mux[NUM_FM_PORTS];
93 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
94 * that the mapping must be determined dynamically, or that the lane maps to
95 * something other than a board slot
97 static u8 lane_to_slot[] = {
98 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
102 * Set the board muxing for a given MAC
104 * The MDIO layer calls this function every time it wants to talk to a PHY.
106 void hydra_mux_mdio(u8 mask, u8 val)
108 clrsetbits_8(&pixis->brdcfg1, mask, val);
114 struct mii_dev *realbus;
117 static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
120 struct hydra_mdio *priv = bus->priv;
122 hydra_mux_mdio(priv->mask, priv->val);
124 return priv->realbus->read(priv->realbus, addr, devad, regnum);
127 static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
128 int regnum, u16 value)
130 struct hydra_mdio *priv = bus->priv;
132 hydra_mux_mdio(priv->mask, priv->val);
134 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
137 static int hydra_mdio_reset(struct mii_dev *bus)
139 struct hydra_mdio *priv = bus->priv;
141 return priv->realbus->reset(priv->realbus);
144 static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
146 struct mii_dev *bus = miiphy_get_dev_by_name(name);
147 struct hydra_mdio *priv = bus->priv;
153 static int hydra_mdio_init(char *realbusname, char *fakebusname)
155 struct hydra_mdio *hmdio;
156 struct mii_dev *bus = mdio_alloc();
159 printf("Failed to allocate Hydra MDIO bus\n");
163 hmdio = malloc(sizeof(*hmdio));
165 printf("Failed to allocate Hydra private data\n");
170 bus->read = hydra_mdio_read;
171 bus->write = hydra_mdio_write;
172 bus->reset = hydra_mdio_reset;
173 sprintf(bus->name, fakebusname);
175 hmdio->realbus = miiphy_get_dev_by_name(realbusname);
177 if (!hmdio->realbus) {
178 printf("No bus with name %s\n", realbusname);
186 return mdio_register(bus);
190 * Given an alias or a path for a node, set the mux value of that node.
192 * If 'alias' is not a valid alias, then it is treated as a full path to the
193 * node. No error checking is performed.
195 * This function is normally called to set the fsl,hydra-mdio-muxval property
196 * of a virtual MDIO node.
198 static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
200 const char *path = fdt_get_alias(fdt, alias);
205 do_fixup_by_path(fdt, path, "reg",
206 &mux, sizeof(mux), 1);
207 do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
208 &mux, sizeof(mux), 1);
212 * Given the following ...
214 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
215 * compatible string and 'addr' physical address)
219 * ... update the phy-handle property of the Ethernet node to point to the
220 * right PHY. This assumes that we already know the PHY for each port. That
221 * information is stored in mdio_mux[].
223 * The offset of the Fman Ethernet node is also passed in for convenience, but
224 * it is not used, and we recalculate the offset anyway.
226 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
227 * Inside the Fman, "ports" are things that connect to MACs. We only call them
228 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
229 * and ports are the same thing.
231 * Note that this code would be cleaner if had a function called
232 * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[]
233 * array. That's because all we're doing is figuring out the PHY address for
234 * a given Fman MAC and writing it to the device tree. Well, we already did
235 * the hard work to figure that out in board_eth_init(), so it's silly to
238 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
239 enum fm_port port, int offset)
241 unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
244 if (port == FM1_10GEC1) {
246 int lane = serdes_get_first_lane(XAUI_FM1);
248 /* The XAUI PHY is identified by the slot */
249 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
250 fdt_set_phy_handle(fdt, compat, addr, phy);
255 if (mux == BRDCFG1_EMI1_SEL_RGMII) {
257 /* The RGMII PHY is identified by the MAC connected to it */
258 sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
259 fdt_set_phy_handle(fdt, compat, addr, phy);
262 /* If it's not RGMII or XGMII, it must be SGMII */
264 /* The SGMII PHY is identified by the MAC connected to it */
265 sprintf(phy, "phy_sgmii_%x",
266 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
267 fdt_set_phy_handle(fdt, compat, addr, phy);
271 #define PIXIS_SW2_LANE_23_SEL 0x80
272 #define PIXIS_SW2_LANE_45_SEL 0x40
273 #define PIXIS_SW2_LANE_67_SEL_MASK 0x30
274 #define PIXIS_SW2_LANE_67_SEL_5 0x00
275 #define PIXIS_SW2_LANE_67_SEL_6 0x20
276 #define PIXIS_SW2_LANE_67_SEL_7 0x10
277 #define PIXIS_SW2_LANE_8_SEL 0x08
278 #define PIXIS_SW2_LANE_1617_SEL 0x04
281 * Initialize the lane_to_slot[] array.
283 * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
284 * slots is hard-coded. On the Hydra board, however, the mapping is controlled
285 * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
288 static void initialize_lane_to_slot(void)
290 u8 sw2 = in_8(&PIXIS_SW(2));
292 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
293 lane_to_slot[3] = lane_to_slot[2];
295 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
296 lane_to_slot[5] = lane_to_slot[4];
298 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
299 case PIXIS_SW2_LANE_67_SEL_5:
302 case PIXIS_SW2_LANE_67_SEL_6:
305 case PIXIS_SW2_LANE_67_SEL_7:
309 lane_to_slot[7] = lane_to_slot[6];
311 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
313 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
314 lane_to_slot[17] = lane_to_slot[16];
317 #endif /* #ifdef CONFIG_FMAN_ENET */
320 * Configure the status for the virtual MDIO nodes
322 * Rather than create the virtual MDIO nodes from scratch for each active
323 * virtual MDIO, we expect the DTS to have the nodes defined already, and we
324 * only enable the ones that are actually active.
326 * We assume that the DTS already hard-codes the status for all the
327 * virtual MDIO nodes to "disabled", so all we need to do is enable the
330 * For SGMII, we also need to set the mux value in the node.
332 void fdt_fixup_board_enet(void *fdt)
334 #ifdef CONFIG_FMAN_ENET
338 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
339 int idx = i - FM1_DTSEC1;
341 switch (fm_info_get_enet_if(i)) {
342 case PHY_INTERFACE_MODE_SGMII:
343 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
345 fdt_status_okay_by_alias(fdt, "emi1_sgmii");
346 /* Also set the MUX value */
347 fdt_set_mdio_mux(fdt, "emi1_sgmii",
351 case PHY_INTERFACE_MODE_RGMII:
352 fdt_status_okay_by_alias(fdt, "emi1_rgmii");
359 lane = serdes_get_first_lane(XAUI_FM1);
361 fdt_status_okay_by_alias(fdt, "emi2_xgmii");
365 int board_eth_init(bd_t *bis)
367 #ifdef CONFIG_FMAN_ENET
368 struct fsl_pq_mdio_info dtsec_mdio_info;
369 struct tgec_mdio_info tgec_mdio_info;
370 unsigned int i, slot;
374 printf("Initializing Fman\n");
376 initialize_lane_to_slot();
378 /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
379 setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
381 memset(mdio_mux, 0, sizeof(mdio_mux));
383 dtsec_mdio_info.regs =
384 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
385 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
387 /* Register the real 1G MDIO bus */
388 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
390 tgec_mdio_info.regs =
391 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
392 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
394 /* Register the real 10G MDIO bus */
395 fm_tgec_mdio_init(bis, &tgec_mdio_info);
397 /* Register the three virtual MDIO front-ends */
398 hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
399 hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
402 * Program the DTSEC PHY addresses assuming that they are all SGMII.
403 * For any DTSEC that's RGMII, we'll override its PHY address later.
404 * We assume that DTSEC5 is only used for RGMII.
406 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
407 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
408 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
409 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
411 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
412 int idx = i - FM1_DTSEC1;
414 switch (fm_info_get_enet_if(i)) {
415 case PHY_INTERFACE_MODE_SGMII:
416 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
419 slot = lane_to_slot[lane];
420 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
423 /* Always DTSEC5 on Bank 3 */
424 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
428 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
432 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
436 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
440 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
445 hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
446 mdio_mux[i].mask, mdio_mux[i].val);
448 miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
450 case PHY_INTERFACE_MODE_RGMII:
452 * If DTSEC4 is RGMII, then it's routed via via EC1 to
453 * the first on-board RGMII port. If DTSEC5 is RGMII,
454 * then it's routed via via EC2 to the second on-board
455 * RGMII port. The other DTSECs cannot be routed to
458 fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
459 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
460 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
462 hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
463 mdio_mux[i].mask, mdio_mux[i].val);
465 miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
467 case PHY_INTERFACE_MODE_NONE:
468 fm_info_set_phy_address(i, 0);
471 printf("Fman1: DTSEC%u set to unknown interface %i\n",
472 idx + 1, fm_info_get_enet_if(i));
473 fm_info_set_phy_address(i, 0);
478 bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
479 set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
482 * For 10G, we only support one XAUI card per Fman. If present, then we
483 * force its routing and never touch those bits again, which removes the
484 * need for Linux to do any muxing. This works because of the way
485 * BRDCFG1 is defined, but it's a bit hackish.
487 * The PHY address for the XAUI card depends on which slot it's in. The
488 * macros we use imply that the PHY address is based on which FM, but
489 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
490 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
491 * check the actual slot and just use the macros as-is, even though
492 * the P3041 and P5020 only have one Fman.
494 lane = serdes_get_first_lane(XAUI_FM1);
496 slot = lane_to_slot[lane];
498 /* XAUI card is in slot 1 */
499 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
500 BRDCFG1_EMI2_SEL_SLOT1);
501 fm_info_set_phy_address(FM1_10GEC1,
502 CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
504 /* XAUI card is in slot 2 */
505 clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
506 BRDCFG1_EMI2_SEL_SLOT2);
507 fm_info_set_phy_address(FM1_10GEC1,
508 CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
512 fm_info_set_mdio(FM1_10GEC1,
513 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
518 return pci_eth_init(bis);