1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
10 #include <asm/processor.h>
11 #include <asm/cache.h>
12 #include <asm/immap_85xx.h>
13 #include <asm/fsl_law.h>
14 #include <fsl_ddr_sdram.h>
15 #include <asm/fsl_serdes.h>
16 #include <asm/fsl_portals.h>
17 #include <asm/fsl_liodn.h>
24 #include "../common/ngpixis.h"
25 #include "../common/fman.h"
26 #include <fsl_dtsec.h>
28 #define EMI_NONE 0xffffffff
29 #define EMI_MASK 0xf0000000
30 #define EMI1_RGMII 0x0
31 #define EMI1_SLOT3 0x80000000 /* bank1 EFGH */
32 #define EMI1_SLOT4 0x40000000 /* bank2 ABCD */
33 #define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */
34 #define EMI2_SLOT4 0x10000000 /* bank2 ABCD */
35 #define EMI2_SLOT5 0x30000000 /* bank3 ABCD */
36 #define EMI1_MASK 0xc0000000
37 #define EMI2_MASK 0x30000000
39 #define PHY_BASE_ADDR 0x00
40 #define PHY_BASE_ADDR_SLOT5 0x10
42 static int mdio_mux[NUM_FM_PORTS];
44 static char *mdio_names[16] = {
58 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
59 * that the mapping must be determined dynamically, or that the lane maps to
60 * something other than a board slot.
62 static u8 lane_to_slot[] = {
63 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
66 static char *p4080ds_mdio_name_for_muxval(u32 muxval)
68 return mdio_names[(muxval & EMI_MASK) >> 28];
71 struct mii_dev *mii_dev_for_muxval(u32 muxval)
74 char *name = p4080ds_mdio_name_for_muxval(muxval);
77 printf("No bus for muxval %x\n", muxval);
81 bus = miiphy_get_dev_by_name(name);
84 printf("No bus by name %s\n", name);
91 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
92 int board_phy_config(struct phy_device *phydev)
94 if (phydev->drv->config)
95 phydev->drv->config(phydev);
96 if (phydev->drv->uid == PHY_UID_TN2020) {
97 unsigned long timeout = 1 * 1000; /* 1 seconds */
98 enum srds_prtcl device;
101 * Wait for the XAUI to come out of reset. This is when it
102 * starts transmitting alignment signals.
105 int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
107 printf("TN2020: Error reading from PHY at "
108 "address %u\n", phydev->addr);
112 * Note that we've never actually seen
113 * MDIO_CTRL1_RESET set to 1.
115 if ((reg & MDIO_CTRL1_RESET) == 0)
121 printf("TN2020: Timeout waiting for PHY at address %u "
122 " to reset.\n", phydev->addr);
125 switch (phydev->addr) {
126 case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
129 case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
136 serdes_reset_rx(device);
143 struct p4080ds_mdio {
145 struct mii_dev *realbus;
148 static void p4080ds_mux_mdio(u32 muxval)
150 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
151 uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
154 out_be32(&pgpio->gpdat, gpioval);
157 static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
160 struct p4080ds_mdio *priv = bus->priv;
162 p4080ds_mux_mdio(priv->muxval);
164 return priv->realbus->read(priv->realbus, addr, devad, regnum);
167 static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
168 int regnum, u16 value)
170 struct p4080ds_mdio *priv = bus->priv;
172 p4080ds_mux_mdio(priv->muxval);
174 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
177 static int p4080ds_mdio_reset(struct mii_dev *bus)
179 struct p4080ds_mdio *priv = bus->priv;
181 return priv->realbus->reset(priv->realbus);
184 static int p4080ds_mdio_init(char *realbusname, u32 muxval)
186 struct p4080ds_mdio *pmdio;
187 struct mii_dev *bus = mdio_alloc();
190 printf("Failed to allocate P4080DS MDIO bus\n");
194 pmdio = malloc(sizeof(*pmdio));
196 printf("Failed to allocate P4080DS private data\n");
201 bus->read = p4080ds_mdio_read;
202 bus->write = p4080ds_mdio_write;
203 bus->reset = p4080ds_mdio_reset;
204 sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
206 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
208 if (!pmdio->realbus) {
209 printf("No bus with name %s\n", realbusname);
215 pmdio->muxval = muxval;
218 return mdio_register(bus);
221 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
222 enum fm_port port, int offset)
224 if (mdio_mux[port] == EMI1_RGMII)
225 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
227 if (mdio_mux[port] == EMI1_SLOT3) {
228 int idx = port - FM2_DTSEC1 + 5;
231 sprintf(phy, "phy%d_slot3", idx);
233 fdt_set_phy_handle(blob, prop, pa, phy);
237 void fdt_fixup_board_enet(void *fdt)
242 * P4080DS can be configured in many different ways, supporting a number
243 * of combinations of ethernet devices and phy types. In order to
244 * have just one device tree for all of those configurations, we fix up
245 * the tree here. By default, the device tree configures FM1 and FM2
246 * for SGMII, and configures XAUI on both 10G interfaces. So we have
247 * a number of different variables to track:
249 * 1) Whether the device is configured at all. Whichever devices are
250 * not enabled should be disabled by setting the "status" property
252 * 2) What the PHY interface is. If this is an RGMII connection,
253 * we should change the "phy-connection-type" property to
255 * 3) Which PHY is being used. Because the MDIO buses are muxed,
256 * we need to redirect the "phy-handle" property to point at the
257 * PHY on the right slot/bus.
260 /* We've got six MDIO nodes that may or may not need to exist */
261 fdt_status_disabled_by_alias(fdt, "emi1_slot3");
262 fdt_status_disabled_by_alias(fdt, "emi1_slot4");
263 fdt_status_disabled_by_alias(fdt, "emi1_slot5");
264 fdt_status_disabled_by_alias(fdt, "emi2_slot4");
265 fdt_status_disabled_by_alias(fdt, "emi2_slot5");
267 for (i = 0; i < NUM_FM_PORTS; i++) {
268 switch (mdio_mux[i]) {
270 fdt_status_okay_by_alias(fdt, "emi1_slot3");
273 fdt_status_okay_by_alias(fdt, "emi1_slot4");
276 fdt_status_okay_by_alias(fdt, "emi1_slot5");
279 fdt_status_okay_by_alias(fdt, "emi2_slot4");
282 fdt_status_okay_by_alias(fdt, "emi2_slot5");
288 int board_eth_init(bd_t *bis)
290 #ifdef CONFIG_FMAN_ENET
291 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
293 struct fsl_pq_mdio_info dtsec_mdio_info;
294 struct tgec_mdio_info tgec_mdio_info;
297 /* Initialize the mdio_mux array so we can recognize empty elements */
298 for (i = 0; i < NUM_FM_PORTS; i++)
299 mdio_mux[i] = EMI_NONE;
301 /* The first 4 GPIOs are outputs to control MDIO bus muxing */
302 out_be32(&pgpio->gpdir, EMI_MASK);
304 dtsec_mdio_info.regs =
305 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
306 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
308 /* Register the 1G MDIO bus */
309 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
311 tgec_mdio_info.regs =
312 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
313 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
315 /* Register the 10G MDIO bus */
316 fm_tgec_mdio_init(bis, &tgec_mdio_info);
318 /* Register the 6 muxing front-ends to the MDIO buses */
319 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
320 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
321 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
322 p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
323 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
324 p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
326 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
327 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
328 fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
329 fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
330 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
332 #if (CONFIG_SYS_NUM_FMAN == 2)
333 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
334 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
335 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
336 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
337 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
340 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
341 int idx = i - FM1_DTSEC1, lane, slot;
342 switch (fm_info_get_enet_if(i)) {
343 case PHY_INTERFACE_MODE_SGMII:
344 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
347 slot = lane_to_slot[lane];
350 mdio_mux[i] = EMI1_SLOT3;
352 mii_dev_for_muxval(mdio_mux[i]));
355 mdio_mux[i] = EMI1_SLOT4;
357 mii_dev_for_muxval(mdio_mux[i]));
360 mdio_mux[i] = EMI1_SLOT5;
362 mii_dev_for_muxval(mdio_mux[i]));
366 case PHY_INTERFACE_MODE_RGMII:
367 fm_info_set_phy_address(i, 0);
368 mdio_mux[i] = EMI1_RGMII;
370 mii_dev_for_muxval(mdio_mux[i]));
376 bus = mii_dev_for_muxval(EMI1_SLOT5);
377 set_sgmii_phy(bus, FM1_DTSEC1,
378 CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
380 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
381 int idx = i - FM1_10GEC1, lane, slot;
382 switch (fm_info_get_enet_if(i)) {
383 case PHY_INTERFACE_MODE_XGMII:
384 lane = serdes_get_first_lane(XAUI_FM1 + idx);
387 slot = lane_to_slot[lane];
390 mdio_mux[i] = EMI2_SLOT4;
392 mii_dev_for_muxval(mdio_mux[i]));
395 mdio_mux[i] = EMI2_SLOT5;
397 mii_dev_for_muxval(mdio_mux[i]));
406 #if (CONFIG_SYS_NUM_FMAN == 2)
407 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
408 int idx = i - FM2_DTSEC1, lane, slot;
409 switch (fm_info_get_enet_if(i)) {
410 case PHY_INTERFACE_MODE_SGMII:
411 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
414 slot = lane_to_slot[lane];
417 mdio_mux[i] = EMI1_SLOT3;
419 mii_dev_for_muxval(mdio_mux[i]));
422 mdio_mux[i] = EMI1_SLOT4;
424 mii_dev_for_muxval(mdio_mux[i]));
427 mdio_mux[i] = EMI1_SLOT5;
429 mii_dev_for_muxval(mdio_mux[i]));
433 case PHY_INTERFACE_MODE_RGMII:
434 fm_info_set_phy_address(i, 0);
435 mdio_mux[i] = EMI1_RGMII;
437 mii_dev_for_muxval(mdio_mux[i]));
444 bus = mii_dev_for_muxval(EMI1_SLOT3);
445 set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
446 bus = mii_dev_for_muxval(EMI1_SLOT4);
447 set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
449 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
450 int idx = i - FM2_10GEC1, lane, slot;
451 switch (fm_info_get_enet_if(i)) {
452 case PHY_INTERFACE_MODE_XGMII:
453 lane = serdes_get_first_lane(XAUI_FM2 + idx);
456 slot = lane_to_slot[lane];
459 mdio_mux[i] = EMI2_SLOT4;
461 mii_dev_for_muxval(mdio_mux[i]));
464 mdio_mux[i] = EMI2_SLOT5;
466 mii_dev_for_muxval(mdio_mux[i]));
477 #endif /* CONFIG_FMAN_ENET */
479 return pci_eth_init(bis);