2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
3 * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file handles the board muxing between the Fman Ethernet MACs and
10 * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference
11 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
12 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
13 * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
14 * and 5 1G interfaces and 10G interface per FMan. Based on the options in
15 * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time.
17 * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
18 * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
19 * always the same (0). The value for SGMII depends on which slot the riser is
20 * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
21 * the value is based on which slot the XAUI is inserted in.
23 * The SERDES configuration is used to determine where the SGMII and XAUI cards
24 * exist, and also which Fman's MACs are routed to which PHYs. So for a given
25 * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
26 * to PHYs dynamically.
29 * This file also updates the device tree in three ways:
31 * 1) The status of each virtual MDIO node that is referenced by an Ethernet
32 * node is set to "okay".
34 * 2) The phy-handle property of each active Ethernet MAC node is set to the
35 * appropriate PHY node.
37 * 3) The "mux value" for each virtual MDIO node is set to the correct value,
38 * if necessary. Some virtual MDIO nodes do not have configurable mux
39 * values, so those values are hard-coded in the DTS. On the HYDRA board,
40 * the virtual MDIO node for the SGMII card needs to be updated.
42 * For all this to work, the device tree needs to have the following:
44 * 1) An alias for each PHY node that an Ethernet node could be routed to.
46 * 2) An alias for each real and virtual MDIO node that is disabled by default
47 * and might need to be enabled, and also might need to have its mux-value
53 #include <asm/fsl_serdes.h>
57 #include <fdt_support.h>
58 #include <asm/fsl_dtsec.h>
60 #include "../common/ngpixis.h"
61 #include "../common/fman.h"
63 #ifdef CONFIG_FMAN_ENET
65 #define BRDCFG1_EMI1_SEL_MASK 0x70
66 #define BRDCFG1_EMI1_SEL_SLOT1 0x10
67 #define BRDCFG1_EMI1_SEL_SLOT2 0x20
68 #define BRDCFG1_EMI1_SEL_SLOT5 0x30
69 #define BRDCFG1_EMI1_SEL_SLOT6 0x40
70 #define BRDCFG1_EMI1_SEL_SLOT7 0x50
71 #define BRDCFG1_EMI1_SEL_SLOT3 0x60
72 #define BRDCFG1_EMI1_SEL_RGMII 0x00
73 #define BRDCFG1_EMI1_EN 0x08
74 #define BRDCFG1_EMI2_SEL_MASK 0x06
75 #define BRDCFG1_EMI2_SEL_SLOT1 0x00
76 #define BRDCFG1_EMI2_SEL_SLOT2 0x02
78 #define BRDCFG2_REG_GPIO_SEL 0x20
81 * BRDCFG1 mask and value for each MAC
83 * This array contains the BRDCFG1 values (in mask/val format) that route the
84 * MDIO bus to a particular RGMII or SGMII PHY.
89 } mdio_mux[NUM_FM_PORTS];
92 * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
93 * that the mapping must be determined dynamically, or that the lane maps to
94 * something other than a board slot
96 static u8 lane_to_slot[] = {
97 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0
101 * Set the board muxing for a given MAC
103 * The MDIO layer calls this function every time it wants to talk to a PHY.
105 void super_hydra_mux_mdio(u8 mask, u8 val)
107 clrsetbits_8(&pixis->brdcfg1, mask, val);
110 struct super_hydra_mdio {
113 struct mii_dev *realbus;
116 static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
119 struct super_hydra_mdio *priv = bus->priv;
121 super_hydra_mux_mdio(priv->mask, priv->val);
123 return priv->realbus->read(priv->realbus, addr, devad, regnum);
126 static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
127 int regnum, u16 value)
129 struct super_hydra_mdio *priv = bus->priv;
131 super_hydra_mux_mdio(priv->mask, priv->val);
133 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
136 static int super_hydra_mdio_reset(struct mii_dev *bus)
138 struct super_hydra_mdio *priv = bus->priv;
140 return priv->realbus->reset(priv->realbus);
143 static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val)
145 struct mii_dev *bus = miiphy_get_dev_by_name(name);
146 struct super_hydra_mdio *priv = bus->priv;
152 static int super_hydra_mdio_init(char *realbusname, char *fakebusname)
154 struct super_hydra_mdio *hmdio;
155 struct mii_dev *bus = mdio_alloc();
158 printf("Failed to allocate Hydra MDIO bus\n");
162 hmdio = malloc(sizeof(*hmdio));
164 printf("Failed to allocate Hydra private data\n");
169 bus->read = super_hydra_mdio_read;
170 bus->write = super_hydra_mdio_write;
171 bus->reset = super_hydra_mdio_reset;
172 sprintf(bus->name, fakebusname);
174 hmdio->realbus = miiphy_get_dev_by_name(realbusname);
176 if (!hmdio->realbus) {
177 printf("No bus with name %s\n", realbusname);
185 return mdio_register(bus);
189 * Given the following ...
191 * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
192 * compatible string and 'addr' physical address)
196 * ... update the phy-handle property of the Ethernet node to point to the
197 * right PHY. This assumes that we already know the PHY for each port. That
198 * information is stored in mdio_mux[].
200 * The offset of the Fman Ethernet node is also passed in for convenience, but
203 * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
204 * Inside the Fman, "ports" are things that connect to MACs. We only call them
205 * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
206 * and ports are the same thing.
208 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
209 enum fm_port port, int offset)
211 enum srds_prtcl device;
215 /* RGMII and XGMII are already mapped correctly in the DTS */
217 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
218 device = serdes_device_from_fm_port(port);
219 lane = serdes_get_first_lane(device);
220 slot = lane_to_slot[lane];
221 phy = fm_info_get_phy_address(port);
223 sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
224 fdt_set_phy_handle(fdt, compat, addr, alias);
228 #define PIXIS_SW2_LANE_23_SEL 0x80
229 #define PIXIS_SW2_LANE_45_SEL 0x40
230 #define PIXIS_SW2_LANE_67_SEL_MASK 0x30
231 #define PIXIS_SW2_LANE_67_SEL_5 0x00
232 #define PIXIS_SW2_LANE_67_SEL_6 0x20
233 #define PIXIS_SW2_LANE_67_SEL_7 0x10
234 #define PIXIS_SW2_LANE_8_SEL 0x08
235 #define PIXIS_SW2_LANE_1617_SEL 0x04
236 #define PIXIS_SW11_LANE_9_SEL 0x04
238 * Initialize the lane_to_slot[] array.
240 * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
241 * slots is hard-coded. On the Hydra board, however, the mapping is controlled
242 * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
245 static void initialize_lane_to_slot(void)
247 u8 sw2 = in_8(&PIXIS_SW(2));
248 /* SW11 appears in the programming model as SW9 */
249 u8 sw11 = in_8(&PIXIS_SW(9));
251 lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
252 lane_to_slot[3] = lane_to_slot[2];
254 lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
255 lane_to_slot[5] = lane_to_slot[4];
257 switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
258 case PIXIS_SW2_LANE_67_SEL_5:
261 case PIXIS_SW2_LANE_67_SEL_6:
264 case PIXIS_SW2_LANE_67_SEL_7:
268 lane_to_slot[7] = lane_to_slot[6];
270 lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
271 lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3;
273 lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
274 lane_to_slot[17] = lane_to_slot[16];
277 #endif /* #ifdef CONFIG_FMAN_ENET */
280 * Configure the status for the virtual MDIO nodes
282 * Rather than create the virtual MDIO nodes from scratch for each active
283 * virtual MDIO, we expect the DTS to have the nodes defined already, and we
284 * only enable the ones that are actually active.
286 * We assume that the DTS already hard-codes the status for all the
287 * virtual MDIO nodes to "disabled", so all we need to do is enable the
290 void fdt_fixup_board_enet(void *fdt)
292 #ifdef CONFIG_FMAN_ENET
296 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
297 int idx = i - FM1_DTSEC1;
299 switch (fm_info_get_enet_if(i)) {
300 case PHY_INTERFACE_MODE_SGMII:
301 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
305 slot = lane_to_slot[lane];
306 sprintf(alias, "hydra_sg_slot%u", slot);
307 fdt_status_okay_by_alias(fdt, alias);
308 debug("Enabled MDIO node %s (slot %i)\n",
312 case PHY_INTERFACE_MODE_RGMII:
313 fdt_status_okay_by_alias(fdt, "hydra_rg");
314 debug("Enabled MDIO node hydra_rg\n");
321 lane = serdes_get_first_lane(XAUI_FM1);
325 slot = lane_to_slot[lane];
326 sprintf(alias, "hydra_xg_slot%u", slot);
327 fdt_status_okay_by_alias(fdt, alias);
328 debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
331 #if CONFIG_SYS_NUM_FMAN == 2
332 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
333 int idx = i - FM2_DTSEC1;
335 switch (fm_info_get_enet_if(i)) {
336 case PHY_INTERFACE_MODE_SGMII:
337 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
341 slot = lane_to_slot[lane];
342 sprintf(alias, "hydra_sg_slot%u", slot);
343 fdt_status_okay_by_alias(fdt, alias);
344 debug("Enabled MDIO node %s (slot %i)\n",
348 case PHY_INTERFACE_MODE_RGMII:
349 fdt_status_okay_by_alias(fdt, "hydra_rg");
350 debug("Enabled MDIO node hydra_rg\n");
357 lane = serdes_get_first_lane(XAUI_FM2);
361 slot = lane_to_slot[lane];
362 sprintf(alias, "hydra_xg_slot%u", slot);
363 fdt_status_okay_by_alias(fdt, alias);
364 debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
366 #endif /* CONFIG_SYS_NUM_FMAN == 2 */
367 #endif /* CONFIG_FMAN_ENET */
371 * Mapping of SerDes Protocol to MDIO MUX value and PHY address.
374 * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
375 * Mux Phy | Mux Phy | Mux Phy | Mux Phy
376 * Value Addr | Value Addr | Value Addr | Value Addr
377 * 0x00 2 1c | 2 1d | 2 1e | 2 1f
379 * 0x02 | | 3 1c | 3 1d
380 * 0x03 2 1c | 2 1d | 2 1e | 2 1f
381 * 0x04 2 1c | 2 1d | 2 1e | 2 1f
382 * 0x05 | | 3 1c | 3 1d
383 * 0x06 2 1c | 2 1d | 2 1e | 2 1f
385 * 0x11 2 1c | 2 1d | 2 1e | 2 1f
386 * 0x2a 2 | | 2 1e | 2 1f
387 * 0x34 6 1c | 6 1d | 4 1e | 4 1f
388 * 0x35 | | 3 1c | 3 1d
389 * 0x36 6 1c | 6 1d | 4 1e | 4 1f
392 * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
393 * EMI1 | EMI1 | EMI1 | EMI1
394 * Mux Phy | Mux Phy | Mux Phy | Mux Phy
395 * Value Addr | Value Addr | Value Addr | Value Addr
396 * 0x00 | | 6 1c | 6 1d
398 * 0x02 | | 6 1c | 6 1d
399 * 0x03 3 1c | 3 1d | 6 1c | 6 1d
400 * 0x04 3 1c | 3 1d | 6 1c | 6 1d
401 * 0x05 | | 6 1c | 6 1d
402 * 0x06 | | 6 1c | 6 1d
411 int board_eth_init(bd_t *bis)
413 #ifdef CONFIG_FMAN_ENET
414 struct fsl_pq_mdio_info dtsec_mdio_info;
415 struct tgec_mdio_info tgec_mdio_info;
416 unsigned int i, slot;
418 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
419 int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
420 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
422 printf("Initializing Fman\n");
424 initialize_lane_to_slot();
426 /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
427 setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
429 memset(mdio_mux, 0, sizeof(mdio_mux));
431 dtsec_mdio_info.regs =
432 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
433 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
435 /* Register the real 1G MDIO bus */
436 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
438 tgec_mdio_info.regs =
439 (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
440 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
442 /* Register the real 10G MDIO bus */
443 fm_tgec_mdio_init(bis, &tgec_mdio_info);
445 /* Register the three virtual MDIO front-ends */
446 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
447 "SUPER_HYDRA_RGMII_MDIO");
448 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
449 "SUPER_HYDRA_FM1_SGMII_MDIO");
450 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
451 "SUPER_HYDRA_FM2_SGMII_MDIO");
452 super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
453 "SUPER_HYDRA_FM3_SGMII_MDIO");
454 super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
455 "SUPER_HYDRA_FM1_TGEC_MDIO");
456 super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
457 "SUPER_HYDRA_FM2_TGEC_MDIO");
460 * Program the DTSEC PHY addresses assuming that they are all SGMII.
461 * For any DTSEC that's RGMII, we'll override its PHY address later.
462 * We assume that DTSEC5 is only used for RGMII.
464 fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
465 fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
466 fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
468 #if (CONFIG_SYS_NUM_FMAN == 2)
469 fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
470 fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
471 fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
472 fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
473 fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
476 switch (srds_prtcl) {
485 fm_info_set_phy_address(FM1_DTSEC3,
486 CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
487 fm_info_set_phy_address(FM1_DTSEC4,
488 CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
495 fm_info_set_phy_address(FM1_DTSEC3,
496 CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
497 fm_info_set_phy_address(FM1_DTSEC4,
498 CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
501 printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl);
505 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
506 int idx = i - FM1_DTSEC1;
508 switch (fm_info_get_enet_if(i)) {
509 case PHY_INTERFACE_MODE_SGMII:
510 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
513 slot = lane_to_slot[lane];
514 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
515 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
519 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
523 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
527 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
531 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
535 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
539 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
544 super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO",
545 mdio_mux[i].mask, mdio_mux[i].val);
547 miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
549 case PHY_INTERFACE_MODE_RGMII:
551 * FM1 DTSEC5 is routed via EC1 to the first on-board
552 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
553 * second on-board RGMII port. The other DTSECs cannot
554 * be routed to RGMII.
556 debug("FM1@DTSEC%u is RGMII at address %u\n",
558 fm_info_set_phy_address(i, 0);
559 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
560 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
562 super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
563 mdio_mux[i].mask, mdio_mux[i].val);
565 miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
567 case PHY_INTERFACE_MODE_NONE:
568 fm_info_set_phy_address(i, 0);
571 printf("Fman1: DTSEC%u set to unknown interface %i\n",
572 idx + 1, fm_info_get_enet_if(i));
573 fm_info_set_phy_address(i, 0);
579 * For 10G, we only support one XAUI card per Fman. If present, then we
580 * force its routing and never touch those bits again, which removes the
581 * need for Linux to do any muxing. This works because of the way
582 * BRDCFG1 is defined, but it's a bit hackish.
584 * The PHY address for the XAUI card depends on which slot it's in. The
585 * macros we use imply that the PHY address is based on which FM, but
586 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
587 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
588 * check the actual slot and just use the macros as-is, even though
589 * the P3041 and P5020 only have one Fman.
591 lane = serdes_get_first_lane(XAUI_FM1);
593 debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
594 mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
595 mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
596 super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
597 mdio_mux[i].mask, mdio_mux[i].val);
600 fm_info_set_mdio(FM1_10GEC1,
601 miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO"));
603 #if (CONFIG_SYS_NUM_FMAN == 2)
604 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
605 int idx = i - FM2_DTSEC1;
607 switch (fm_info_get_enet_if(i)) {
608 case PHY_INTERFACE_MODE_SGMII:
609 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
612 slot = lane_to_slot[lane];
613 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
614 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
618 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
622 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
626 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
630 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
634 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
638 mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
643 if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
644 super_hydra_mdio_set_mux(
645 "SUPER_HYDRA_FM3_SGMII_MDIO",
648 fm_info_set_mdio(i, miiphy_get_dev_by_name(
649 "SUPER_HYDRA_FM3_SGMII_MDIO"));
651 super_hydra_mdio_set_mux(
652 "SUPER_HYDRA_FM2_SGMII_MDIO",
655 fm_info_set_mdio(i, miiphy_get_dev_by_name(
656 "SUPER_HYDRA_FM2_SGMII_MDIO"));
660 case PHY_INTERFACE_MODE_RGMII:
662 * FM1 DTSEC5 is routed via EC1 to the first on-board
663 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
664 * second on-board RGMII port. The other DTSECs cannot
665 * be routed to RGMII.
667 debug("FM2@DTSEC%u is RGMII at address %u\n",
669 fm_info_set_phy_address(i, 1);
670 mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
671 mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
673 super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
674 mdio_mux[i].mask, mdio_mux[i].val);
676 miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
678 case PHY_INTERFACE_MODE_NONE:
679 fm_info_set_phy_address(i, 0);
682 printf("Fman2: DTSEC%u set to unknown interface %i\n",
683 idx + 1, fm_info_get_enet_if(i));
684 fm_info_set_phy_address(i, 0);
690 * For 10G, we only support one XAUI card per Fman. If present, then we
691 * force its routing and never touch those bits again, which removes the
692 * need for Linux to do any muxing. This works because of the way
693 * BRDCFG1 is defined, but it's a bit hackish.
695 * The PHY address for the XAUI card depends on which slot it's in. The
696 * macros we use imply that the PHY address is based on which FM, but
697 * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
698 * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
699 * check the actual slot and just use the macros as-is, even though
700 * the P3041 and P5020 only have one Fman.
702 lane = serdes_get_first_lane(XAUI_FM2);
704 debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
705 mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
706 mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
707 super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
708 mdio_mux[i].mask, mdio_mux[i].val);
711 fm_info_set_mdio(FM2_10GEC1,
712 miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO"));
719 return pci_eth_init(bis);