git.sur5r.net Git - u-boot/blob - board/freescale/corenet_ds/p4080ds_ddr.c

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #include <common.h>
   8 #include <fsl_ddr_sdram.h>
   9
  10 #define CONFIG_SYS_DDR_TIMING_3_1200    0x01030000
  11 #define CONFIG_SYS_DDR_TIMING_0_1200    0xCC550104
  12 #define CONFIG_SYS_DDR_TIMING_1_1200    0x868FAA45
  13 #define CONFIG_SYS_DDR_TIMING_2_1200    0x0FB8A912
  14 #define CONFIG_SYS_DDR_MODE_1_1200      0x00441A40
  15 #define CONFIG_SYS_DDR_MODE_2_1200      0x00100000
  16 #define CONFIG_SYS_DDR_INTERVAL_1200    0x12480100
  17 #define CONFIG_SYS_DDR_CLK_CTRL_1200    0x02800000
  18
  19 #define CONFIG_SYS_DDR_TIMING_3_1000    0x00020000
  20 #define CONFIG_SYS_DDR_TIMING_0_1000    0xCC440104
  21 #define CONFIG_SYS_DDR_TIMING_1_1000    0x727DF944
  22 #define CONFIG_SYS_DDR_TIMING_2_1000    0x0FB088CF
  23 #define CONFIG_SYS_DDR_MODE_1_1000      0x00441830
  24 #define CONFIG_SYS_DDR_MODE_2_1000      0x00080000
  25 #define CONFIG_SYS_DDR_INTERVAL_1000    0x0F3C0100
  26 #define CONFIG_SYS_DDR_CLK_CTRL_1000    0x02800000
  27
  28 #define CONFIG_SYS_DDR_TIMING_3_900     0x00020000
  29 #define CONFIG_SYS_DDR_TIMING_0_900     0xCC440104
  30 #define CONFIG_SYS_DDR_TIMING_1_900     0x616ba844
  31 #define CONFIG_SYS_DDR_TIMING_2_900     0x0fb088ce
  32 #define CONFIG_SYS_DDR_MODE_1_900       0x00441620
  33 #define CONFIG_SYS_DDR_MODE_2_900       0x00080000
  34 #define CONFIG_SYS_DDR_INTERVAL_900     0x0db60100
  35 #define CONFIG_SYS_DDR_CLK_CTRL_900     0x02800000
  36
  37 #define CONFIG_SYS_DDR_TIMING_3_800     0x00020000
  38 #define CONFIG_SYS_DDR_TIMING_0_800     0xcc330104
  39 #define CONFIG_SYS_DDR_TIMING_1_800     0x6f6b4744
  40 #define CONFIG_SYS_DDR_TIMING_2_800     0x0fa888cc
  41 #define CONFIG_SYS_DDR_MODE_1_800       0x00441420
  42 #define CONFIG_SYS_DDR_MODE_2_800       0x00000000
  43 #define CONFIG_SYS_DDR_INTERVAL_800     0x0c300100
  44 #define CONFIG_SYS_DDR_CLK_CTRL_800     0x02800000
  45
  46 #define CONFIG_SYS_DDR_CS0_BNDS         0x000000FF
  47 #define CONFIG_SYS_DDR_CS1_BNDS         0x00000000
  48 #define CONFIG_SYS_DDR_CS2_BNDS         0x000000FF
  49 #define CONFIG_SYS_DDR_CS3_BNDS         0x000000FF
  50 #define CONFIG_SYS_DDR2_CS0_BNDS        0x000000FF
  51 #define CONFIG_SYS_DDR2_CS1_BNDS        0x00000000
  52 #define CONFIG_SYS_DDR2_CS2_BNDS        0x000000FF
  53 #define CONFIG_SYS_DDR2_CS3_BNDS        0x000000FF
  54 #define CONFIG_SYS_DDR_CS0_CONFIG       0xA0044202
  55 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
  56 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80004202
  57 #define CONFIG_SYS_DDR_CS2_CONFIG       0x00000000
  58 #define CONFIG_SYS_DDR_CS3_CONFIG       0x00000000
  59 #define CONFIG_SYS_DDR2_CS0_CONFIG      0x80044202
  60 #define CONFIG_SYS_DDR2_CS1_CONFIG      0x80004202
  61 #define CONFIG_SYS_DDR2_CS2_CONFIG      0x00000000
  62 #define CONFIG_SYS_DDR2_CS3_CONFIG      0x00000000
  63 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
  64 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
  65 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80004202
  66 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
  67 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
  68 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
  69 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
  70 #define CONFIG_SYS_DDR_ZQ_CNTL          0x89080600
  71 #define CONFIG_SYS_DDR_WRLVL_CNTL       0x8675F607
  72 #define CONFIG_SYS_DDR_SDRAM_CFG        0xE7044000
  73 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x24401031
  74 #define CONFIG_SYS_DDR_RCW_1            0x00000000
  75 #define CONFIG_SYS_DDR_RCW_2            0x00000000
  76 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  77
  78 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
  79         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  80         .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  81         .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
  82         .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
  83         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  84         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  85         .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  86         .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
  87         .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
  88         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
  89         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
  90         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
  91         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
  92         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
  93         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
  94         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
  95         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
  96         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  97         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
  98         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  99         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
 100         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 101         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 102         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 103         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 104         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 105         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 106         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 107         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 108 };
 109
 110 fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
 111         .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
 112         .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
 113         .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
 114         .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
 115         .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
 116         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
 117         .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
 118         .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
 119         .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
 120         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
 121         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
 122         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
 123         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
 124         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
 125         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
 126         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
 127         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
 128         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
 129         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
 130         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
 131         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
 132         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 133         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 134         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 135         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 136         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 137         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 138         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 139         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 140 };
 141
 142 fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
 143         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
 144         .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
 145         .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
 146         .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
 147         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
 148         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
 149         .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
 150         .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
 151         .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
 152         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
 153         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
 154         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
 155         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
 156         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
 157         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
 158         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
 159         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
 160         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
 161         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
 162         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
 163         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
 164         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 165         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 166         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 167         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 168         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 169         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 170         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 171         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 172 };
 173
 174 fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
 175         .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
 176         .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
 177         .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
 178         .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
 179         .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
 180         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
 181         .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
 182         .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
 183         .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
 184         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
 185         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
 186         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
 187         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
 188         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
 189         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
 190         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
 191         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
 192         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
 193         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
 194         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
 195         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
 196         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 197         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 198         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 199         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 200         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 201         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 202         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 203         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 204 };
 205
 206 fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
 207         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
 208         .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
 209         .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
 210         .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
 211         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
 212         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
 213         .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
 214         .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
 215         .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
 216         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
 217         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
 218         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
 219         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
 220         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
 221         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
 222         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
 223         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
 224         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
 225         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
 226         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
 227         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
 228         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 229         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 230         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 231         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 232         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 233         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 234         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 235         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 236 };
 237
 238 fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
 239         .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
 240         .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
 241         .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
 242         .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
 243         .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
 244         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
 245         .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
 246         .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
 247         .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
 248         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
 249         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
 250         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
 251         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
 252         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
 253         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
 254         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
 255         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
 256         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
 257         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
 258         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
 259         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
 260         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 261         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 262         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 263         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 264         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 265         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 266         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 267         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 268 };
 269
 270 fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
 271         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
 272         .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
 273         .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
 274         .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
 275         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
 276         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
 277         .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
 278         .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
 279         .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
 280         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
 281         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
 282         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
 283         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
 284         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
 285         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
 286         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
 287         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
 288         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
 289         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
 290         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
 291         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
 292         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 293         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 294         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 295         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 296         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 297         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 298         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 299         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 300 };
 301
 302 fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
 303         .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
 304         .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
 305         .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
 306         .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
 307         .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
 308         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
 309         .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
 310         .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
 311         .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
 312         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
 313         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
 314         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
 315         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
 316         .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
 317         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
 318         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
 319         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
 320         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
 321         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
 322         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
 323         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
 324         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 325         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 326         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 327         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 328         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
 329         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
 330         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 331         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 332 };
 333
 334 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
 335         {750, 850, &ddr_cfg_regs_800},
 336         {850, 950, &ddr_cfg_regs_900},
 337         {950, 1050, &ddr_cfg_regs_1000},
 338         {1050, 1250, &ddr_cfg_regs_1200},
 339         {0, 0, NULL}
 340 };
 341
 342 fixed_ddr_parm_t fixed_ddr_parm_1[] = {
 343         {750, 850, &ddr_cfg_regs_800_2nd},
 344         {850, 950, &ddr_cfg_regs_900_2nd},
 345         {950, 1050, &ddr_cfg_regs_1000_2nd},
 346         {1050, 1250, &ddr_cfg_regs_1200_2nd},
 347         {0, 0, NULL}
 348 };