git.sur5r.net Git - u-boot/blob - board/freescale/corenet_ds/tlb.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/mmu.h>
  28
  29 struct fsl_e_tlb_entry tlb_table[] = {
  30         /* TLB 0 - for temp stack in cache */
  31         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  32                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  33                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  34                       0, 0, BOOKE_PAGESZ_4K, 0),
  35         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  36                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  37                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  38                       0, 0, BOOKE_PAGESZ_4K, 0),
  39         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  40                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  41                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  42                       0, 0, BOOKE_PAGESZ_4K, 0),
  43         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  44                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  45                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  46                       0, 0, BOOKE_PAGESZ_4K, 0),
  47
  48         SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
  49                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  50                       0, 0, BOOKE_PAGESZ_4K, 0),
  51
  52         /* TLB 1 */
  53         /* *I*** - Covers boot page */
  54 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  55         /*
  56          * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  57          * SRAM is at 0xfff00000, it covered the 0xfffff000.
  58          */
  59         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  60                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  61                         0, 0, BOOKE_PAGESZ_1M, 1),
  62 #else
  63         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  64                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  65                       0, 0, BOOKE_PAGESZ_4K, 1),
  66 #endif
  67
  68         /* *I*G* - CCSRBAR */
  69         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  70                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71                       0, 1, BOOKE_PAGESZ_16M, 1),
  72
  73         /* *I*G* - Flash, localbus */
  74         /* This will be changed to *I*G* after relocation to RAM. */
  75         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  76                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  77                       0, 2, BOOKE_PAGESZ_256M, 1),
  78
  79         /* *I*G* - PCI */
  80         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  81                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  82                       0, 3, BOOKE_PAGESZ_1G, 1),
  83
  84         /* *I*G* - PCI */
  85         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  86                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  87                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  88                       0, 4, BOOKE_PAGESZ_256M, 1),
  89
  90         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  91                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  92                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  93                       0, 5, BOOKE_PAGESZ_256M, 1),
  94
  95         /* *I*G* - PCI I/O */
  96         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  97                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  98                       0, 6, BOOKE_PAGESZ_256K, 1),
  99
 100         /* Bman/Qman */
 101         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
 102                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
 103                       0, 9, BOOKE_PAGESZ_1M, 1),
 104         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
 105                       CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
 106                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 107                       0, 10, BOOKE_PAGESZ_1M, 1),
 108         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
 109                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
 110                       0, 11, BOOKE_PAGESZ_1M, 1),
 111         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
 112                       CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
 113                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 114                       0, 12, BOOKE_PAGESZ_1M, 1),
 115 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 116         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 117                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 118                       0, 13, BOOKE_PAGESZ_4M, 1),
 119 #endif
 120 };
 121
 122 int num_tlb_entries = ARRAY_SIZE(tlb_table);