2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
15 #include <environment.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
27 while (in_be32(ptr) & bits) {
32 puts("Error: wait for clear timeout.\n");
37 puts("Board: LS1012AFRDM ");
44 struct mmdc_p_regs *mmdc =
45 (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
47 out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
49 /* configure timing parms */
50 out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
51 out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
52 out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
53 out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
56 out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
57 out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
58 out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
59 out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
61 /* out of reset delays */
62 out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
65 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
66 out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
69 out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
71 /* dram init sequence: update MRs */
72 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
73 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
74 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
76 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
77 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
78 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
79 CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
80 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
82 /* dram init sequence: ZQCL */
83 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
84 CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
85 set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
86 CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
87 FORCE_ZQ_AUTO_CALIBRATION);
89 /* Calibrations now: wr lvl */
90 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
91 CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
93 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
94 set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
98 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
99 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
100 out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
104 /* Calibrations now: Read DQS gating calibration */
105 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
106 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
107 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
108 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
109 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
110 out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
111 set_wait_for_bits_clear(&mmdc->mpdgctrl0,
112 AUTO_RD_DQS_GATING_CALIBRATION_EN,
113 AUTO_RD_DQS_GATING_CALIBRATION_EN);
115 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
118 /* Calibrations now: Read calibration */
119 out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
120 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
121 out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
122 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
123 out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
124 set_wait_for_bits_clear(&mmdc->mprddlhwctl,
125 AUTO_RD_CALIBRATION_EN,
126 AUTO_RD_CALIBRATION_EN);
128 out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
132 out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
133 out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
136 set_wait_for_bits_clear(&mmdc->mdref,
137 CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
140 /* disable CON_REQ */
141 out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
148 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
153 int board_eth_init(bd_t *bis)
155 return pci_eth_init(bis);
158 int board_early_init_f(void)
160 fsl_lsch2_early_init_f();
167 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
169 * Set CCI-400 control override register to enable barrier
172 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
174 #ifdef CONFIG_ENV_IS_NOWHERE
175 gd->env_addr = (ulong)&default_environment[0];
178 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
179 enable_layerscape_ns_access();
185 int ft_board_setup(void *blob, bd_t *bd)
187 arch_fixup_fdt(blob);
189 ft_cpu_setup(blob, bd);