2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #ifdef CONFIG_FSL_LS_PPA
14 #include <asm/arch/ppa.h>
16 #include <asm/arch/fdt.h>
17 #include <asm/arch/mmu.h>
18 #include <asm/arch/soc.h>
24 #include <fsl_esdhc.h>
28 #include "../common/qixis.h"
29 #include "ls1012aqds_qixis.h"
30 #include "ls1012aqds_pfe.h"
32 DECLARE_GLOBAL_DATA_PTR;
39 sw = QIXIS_READ(arch);
40 printf("Board Arch: V%d, ", sw >> 4);
41 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
43 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
45 if (sw & QIXIS_LBMAP_ALTBANK)
50 printf("FPGA: v%d (%s), build %d",
51 (int)QIXIS_READ(scver), qixis_read_tag(buf),
52 (int)qixis_read_minor());
54 /* the timestamp string contains "\n" at the end */
55 printf(" on %s", qixis_read_time(buf));
61 static const struct fsl_mmdc_info mparam = {
62 0x05180000, /* mdctl */
63 0x00030035, /* mdpdc */
64 0x12554000, /* mdotc */
65 0xbabf7954, /* mdcfg0 */
66 0xdb328f64, /* mdcfg1 */
67 0x01ff00db, /* mdcfg2 */
68 0x00001680, /* mdmisc */
69 0x0f3c8000, /* mdref */
70 0x00002000, /* mdrwd */
71 0x00bf1023, /* mdor */
72 0x0000003f, /* mdasp */
73 0x0000022a, /* mpodtctrl */
74 0xa1390003, /* mpzqhwctrl */
79 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
80 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
81 /* This will break-before-make MMU for DDR */
82 update_early_mmu_table();
88 int board_early_init_f(void)
90 fsl_lsch2_early_init_f();
95 #ifdef CONFIG_MISC_INIT_R
98 u8 mux_sdhc_cd = 0x80;
102 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
109 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
110 CONFIG_SYS_CCI400_OFFSET);
112 /* Set CCI-400 control override register to enable barrier
114 out_le32(&cci->ctrl_ord,
115 CCI400_CTRLORD_EN_BARRIER);
117 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
121 #ifdef CONFIG_ENV_IS_NOWHERE
122 gd->env_addr = (ulong)&default_environment[0];
125 #ifdef CONFIG_FSL_LS_PPA
131 int esdhc_status_fixup(void *blob, const char *compat)
133 char esdhc0_path[] = "/soc/esdhc@1560000";
134 char esdhc1_path[] = "/soc/esdhc@1580000";
137 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
141 * The Presence Detect 2 register detects the installation
142 * of cards in various PCI Express or SGMII slots.
144 * STAT_PRS2[7:5]: Specifies the type of card installed in the
145 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
147 card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
149 /* If no adapter is installed in SDHC2, disable SDHC2 */
151 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
152 sizeof("disabled"), 1);
154 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
159 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
160 char *enet_path, char *mdio_path)
162 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
163 &prop_val.busid, PFE_PROP_LEN, 1);
164 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
165 &prop_val.phyid, PFE_PROP_LEN, 1);
166 do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
167 &prop_val.mux_val, PFE_PROP_LEN, 1);
168 do_fixup_by_path(set_blob, enet_path, "phy-mode",
169 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
170 do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
171 &prop_val.phy_mask, PFE_PROP_LEN, 1);
175 static void fdt_fsl_fixup_of_pfe(void *blob)
178 struct pfe_prop_val prop_val;
181 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
182 unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
183 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
184 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
186 for (i = 0; i < NUM_ETH_NODE; i++) {
188 case SERDES_1_G_PROTOCOL:
190 prop_val.busid = cpu_to_fdt32(
192 prop_val.phyid = cpu_to_fdt32(
194 prop_val.mux_val = cpu_to_fdt32(
196 prop_val.phy_mask = cpu_to_fdt32(
197 ETH_1G_MDIO_PHY_MASK);
198 prop_val.phy_mode = "sgmii";
199 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
202 prop_val.busid = cpu_to_fdt32(
204 prop_val.phyid = cpu_to_fdt32(
206 prop_val.mux_val = cpu_to_fdt32(
208 prop_val.phy_mask = cpu_to_fdt32(
209 ETH_1G_MDIO_PHY_MASK);
210 prop_val.phy_mode = "rgmii";
211 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
215 case SERDES_2_5_G_PROTOCOL:
217 prop_val.busid = cpu_to_fdt32(
219 prop_val.phyid = cpu_to_fdt32(
221 prop_val.mux_val = cpu_to_fdt32(
222 ETH_1_2_5G_MDIO_MUX);
223 prop_val.phy_mask = cpu_to_fdt32(
224 ETH_2_5G_MDIO_PHY_MASK);
225 prop_val.phy_mode = "sgmii-2500";
226 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
229 prop_val.busid = cpu_to_fdt32(
231 prop_val.phyid = cpu_to_fdt32(
233 prop_val.mux_val = cpu_to_fdt32(
234 ETH_2_2_5G_MDIO_MUX);
235 prop_val.phy_mask = cpu_to_fdt32(
236 ETH_2_5G_MDIO_PHY_MASK);
237 prop_val.phy_mode = "sgmii-2500";
238 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
243 printf("serdes:[%d]\n", srds_s1);
248 #ifdef CONFIG_OF_BOARD_SETUP
249 int ft_board_setup(void *blob, bd_t *bd)
251 arch_fixup_fdt(blob);
253 ft_cpu_setup(blob, bd);
254 fdt_fsl_fixup_of_pfe(blob);