1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
8 #include <fdt_support.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #ifdef CONFIG_FSL_LS_PPA
13 #include <asm/arch/ppa.h>
15 #include <asm/arch/fdt.h>
16 #include <asm/arch/mmu.h>
17 #include <asm/arch/soc.h>
23 #include <fsl_esdhc.h>
27 #include "../common/qixis.h"
28 #include "ls1012aqds_qixis.h"
29 #include "ls1012aqds_pfe.h"
31 DECLARE_GLOBAL_DATA_PTR;
38 sw = QIXIS_READ(arch);
39 printf("Board Arch: V%d, ", sw >> 4);
40 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
42 sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
44 if (sw & QIXIS_LBMAP_ALTBANK)
49 printf("FPGA: v%d (%s), build %d",
50 (int)QIXIS_READ(scver), qixis_read_tag(buf),
51 (int)qixis_read_minor());
53 /* the timestamp string contains "\n" at the end */
54 printf(" on %s", qixis_read_time(buf));
60 static const struct fsl_mmdc_info mparam = {
61 0x05180000, /* mdctl */
62 0x00030035, /* mdpdc */
63 0x12554000, /* mdotc */
64 0xbabf7954, /* mdcfg0 */
65 0xdb328f64, /* mdcfg1 */
66 0x01ff00db, /* mdcfg2 */
67 0x00001680, /* mdmisc */
68 0x0f3c8000, /* mdref */
69 0x00002000, /* mdrwd */
70 0x00bf1023, /* mdor */
71 0x0000003f, /* mdasp */
72 0x0000022a, /* mpodtctrl */
73 0xa1390003, /* mpzqhwctrl */
78 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
79 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
80 /* This will break-before-make MMU for DDR */
81 update_early_mmu_table();
87 int board_early_init_f(void)
89 fsl_lsch2_early_init_f();
94 #ifdef CONFIG_MISC_INIT_R
97 u8 mux_sdhc_cd = 0x80;
101 i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
108 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
109 CONFIG_SYS_CCI400_OFFSET);
111 /* Set CCI-400 control override register to enable barrier
113 out_le32(&cci->ctrl_ord,
114 CCI400_CTRLORD_EN_BARRIER);
116 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
120 #ifdef CONFIG_ENV_IS_NOWHERE
121 gd->env_addr = (ulong)&default_environment[0];
124 #ifdef CONFIG_FSL_LS_PPA
130 int esdhc_status_fixup(void *blob, const char *compat)
132 char esdhc0_path[] = "/soc/esdhc@1560000";
133 char esdhc1_path[] = "/soc/esdhc@1580000";
136 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
140 * The Presence Detect 2 register detects the installation
141 * of cards in various PCI Express or SGMII slots.
143 * STAT_PRS2[7:5]: Specifies the type of card installed in the
144 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
146 card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
148 /* If no adapter is installed in SDHC2, disable SDHC2 */
150 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
151 sizeof("disabled"), 1);
153 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
158 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
159 char *enet_path, char *mdio_path)
161 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
162 &prop_val.busid, PFE_PROP_LEN, 1);
163 do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
164 &prop_val.phyid, PFE_PROP_LEN, 1);
165 do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
166 &prop_val.mux_val, PFE_PROP_LEN, 1);
167 do_fixup_by_path(set_blob, enet_path, "phy-mode",
168 prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
169 do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
170 &prop_val.phy_mask, PFE_PROP_LEN, 1);
174 static void fdt_fsl_fixup_of_pfe(void *blob)
177 struct pfe_prop_val prop_val;
180 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
181 unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
182 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
183 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
185 for (i = 0; i < NUM_ETH_NODE; i++) {
187 case SERDES_1_G_PROTOCOL:
189 prop_val.busid = cpu_to_fdt32(
191 prop_val.phyid = cpu_to_fdt32(
193 prop_val.mux_val = cpu_to_fdt32(
195 prop_val.phy_mask = cpu_to_fdt32(
196 ETH_1G_MDIO_PHY_MASK);
197 prop_val.phy_mode = "sgmii";
198 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
201 prop_val.busid = cpu_to_fdt32(
203 prop_val.phyid = cpu_to_fdt32(
205 prop_val.mux_val = cpu_to_fdt32(
207 prop_val.phy_mask = cpu_to_fdt32(
208 ETH_1G_MDIO_PHY_MASK);
209 prop_val.phy_mode = "rgmii";
210 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
214 case SERDES_2_5_G_PROTOCOL:
216 prop_val.busid = cpu_to_fdt32(
218 prop_val.phyid = cpu_to_fdt32(
220 prop_val.mux_val = cpu_to_fdt32(
221 ETH_1_2_5G_MDIO_MUX);
222 prop_val.phy_mask = cpu_to_fdt32(
223 ETH_2_5G_MDIO_PHY_MASK);
224 prop_val.phy_mode = "sgmii-2500";
225 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
228 prop_val.busid = cpu_to_fdt32(
230 prop_val.phyid = cpu_to_fdt32(
232 prop_val.mux_val = cpu_to_fdt32(
233 ETH_2_2_5G_MDIO_MUX);
234 prop_val.phy_mask = cpu_to_fdt32(
235 ETH_2_5G_MDIO_PHY_MASK);
236 prop_val.phy_mode = "sgmii-2500";
237 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
242 printf("serdes:[%d]\n", srds_s1);
247 #ifdef CONFIG_OF_BOARD_SETUP
248 int ft_board_setup(void *blob, bd_t *bd)
250 arch_fixup_fdt(blob);
252 ft_cpu_setup(blob, bd);
253 fdt_fsl_fixup_of_pfe(blob);