2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/immap_ls102xa.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/arch/ls102xa_stream_id.h>
13 #include <asm/arch/ls102xa_devdis.h>
14 #include <asm/arch/ls102xa_soc.h>
15 #include <asm/arch/ls102xa_sata.h>
17 #include <fsl_esdhc.h>
18 #include <fsl_immap.h>
24 #include <fsl_validate.h>
25 #include "../common/sleep.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #define DDR_SIZE 0x40000000
34 puts("Board: LS1021AIOT\n");
36 #ifndef CONFIG_QSPI_BOOT
37 struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
40 cpldrev = in_be32(&dcfg->gpporcr1);
42 printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
50 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
51 u32 temp_sdram_cfg, tmp;
53 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
55 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
56 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
58 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
59 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
60 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
61 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
62 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
63 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
65 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
66 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
68 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
69 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
71 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
73 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
75 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
76 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
78 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
80 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
81 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
83 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
85 /* DDR erratum A-009942 */
86 tmp = in_be32(&ddr->debug[28]);
87 out_be32(&ddr->debug[28], tmp | 0x0070006f);
91 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
93 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
98 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
102 gd->ram_size = DDR_SIZE;
106 #ifdef CONFIG_FSL_ESDHC
107 struct fsl_esdhc_cfg esdhc_cfg[1] = {
108 {CONFIG_SYS_FSL_ESDHC_ADDR},
111 int board_mmc_init(bd_t *bis)
113 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
115 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
120 #ifdef CONFIG_TSEC_ENET
121 int board_eth_init(bd_t *bis)
123 struct fsl_pq_mdio_info mdio_info;
124 struct tsec_info_struct tsec_info[4];
128 SET_STD_TSEC_INFO(tsec_info[num], 1);
129 if (is_serdes_configured(SGMII_TSEC1)) {
130 puts("eTSEC1 is in sgmii mode.\n");
131 tsec_info[num].flags |= TSEC_SGMII;
136 SET_STD_TSEC_INFO(tsec_info[num], 2);
137 if (is_serdes_configured(SGMII_TSEC2)) {
138 puts("eTSEC2 is in sgmii mode.\n");
139 tsec_info[num].flags |= TSEC_SGMII;
144 printf("No TSECs initialized\n");
148 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
149 mdio_info.name = DEFAULT_MII_NAME;
150 fsl_pq_mdio_init(bis, &mdio_info);
152 tsec_eth_init(bis, tsec_info, num);
154 return pci_eth_init(bis);
158 int board_early_init_f(void)
160 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
162 #ifdef CONFIG_TSEC_ENET
163 /* clear BD & FR bits for BE BD's and frame data */
164 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
165 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
174 #ifdef CONFIG_SPL_BUILD
175 void board_init_f(ulong dummy)
178 memset(__bss_start, 0, __bss_end - __bss_start);
182 preloader_console_init();
186 /* Allow OCRAM access permission as R/W */
188 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
189 enable_layerscape_ns_access();
192 board_init_r(NULL, 0);
198 #ifndef CONFIG_SYS_FSL_NO_SERDES
202 ls102xa_smmu_stream_id_init();
207 #ifdef CONFIG_BOARD_LATE_INIT
208 int board_late_init(void)
210 #ifdef CONFIG_SCSI_AHCI_PLAT
218 #if defined(CONFIG_MISC_INIT_R)
219 int misc_init_r(void)
221 #ifdef CONFIG_FSL_DEVICE_DISABLE
222 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
226 #ifdef CONFIG_FSL_CAAM
232 int ft_board_setup(void *blob, bd_t *bd)
234 ft_cpu_setup(blob, bd);
237 ft_pci_setup(blob, bd);
243 void flash_write16(u16 val, void *addr)
245 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
247 __raw_writew(shftval, addr);
250 u16 flash_read16(void *addr)
252 u16 val = __raw_readw(addr);
254 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);