2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
14 #include <fsl_esdhc.h>
17 #include "../common/qixis.h"
18 #include "ls1021aqds_qixis.h"
20 DECLARE_GLOBAL_DATA_PTR;
24 MUX_TYPE_SD_PC_SA_SG_SG,
25 MUX_TYPE_SD_PC_SA_PC_SG,
34 puts("Board: LS1021AQDS\n");
36 sw = QIXIS_READ(brdcfg[0]);
37 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
40 printf("vBank: %d\n", sw);
48 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
50 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
51 QIXIS_READ(id), QIXIS_READ(arch));
53 printf("FPGA: v%d (%s), build %d\n",
54 (int)QIXIS_READ(scver), qixis_read_tag(buf),
55 (int)qixis_read_minor());
60 unsigned long get_board_sys_clk(void)
62 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
64 switch (sysclk_conf & 0x0f) {
69 case QIXIS_SYSCLK_100:
71 case QIXIS_SYSCLK_125:
73 case QIXIS_SYSCLK_133:
75 case QIXIS_SYSCLK_150:
77 case QIXIS_SYSCLK_160:
79 case QIXIS_SYSCLK_166:
85 unsigned long get_board_ddr_clk(void)
87 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
89 switch ((ddrclk_conf & 0x30) >> 4) {
90 case QIXIS_DDRCLK_100:
92 case QIXIS_DDRCLK_125:
94 case QIXIS_DDRCLK_133:
102 gd->ram_size = initdram(0);
107 #ifdef CONFIG_FSL_ESDHC
108 struct fsl_esdhc_cfg esdhc_cfg[1] = {
109 {CONFIG_SYS_FSL_ESDHC_ADDR},
112 int board_mmc_init(bd_t *bis)
114 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
116 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
120 int select_i2c_ch_pca9547(u8 ch)
124 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
126 puts("PCA: failed to select proper channel\n");
133 int board_early_init_f(void)
135 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
136 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
138 #ifdef CONFIG_TSEC_ENET
139 out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
140 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
141 out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
144 #ifdef CONFIG_FSL_IFC
145 init_early_memctl_regs();
148 /* Workaround for the issue that DDR could not respond to
149 * barrier transaction which is generated by executing DSB/ISB
150 * instruction. Set CCI-400 control override register to
151 * terminate the barrier transaction. After DDR is initialized,
152 * allow barrier transaction to DDR again */
153 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
158 int config_board_mux(int ctrl_type)
162 reg12 = QIXIS_READ(brdcfg[12]);
165 case MUX_TYPE_SD_PCI4:
168 case MUX_TYPE_SD_PC_SA_SG_SG:
171 case MUX_TYPE_SD_PC_SA_PC_SG:
174 case MUX_TYPE_SD_PC_SG_SG:
178 printf("Wrong mux interface type\n");
182 QIXIS_WRITE(brdcfg[12], reg12);
187 int config_serdes_mux(void)
189 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
192 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
193 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
197 config_board_mux(MUX_TYPE_SD_PCI4);
200 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
203 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
206 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
209 printf("SRDS1 prtcl:0x%x\n", cfg);
218 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
220 /* Set CCI-400 control override register to
221 * enable barrier transaction */
222 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
224 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
226 #ifndef CONFIG_SYS_FSL_NO_SERDES
233 void ft_board_setup(void *blob, bd_t *bd)
235 ft_cpu_setup(blob, bd);
238 u8 flash_read8(void *addr)
240 return __raw_readb(addr + 1);
243 void flash_write16(u16 val, void *addr)
245 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
247 __raw_writew(shftval, addr);
250 u16 flash_read16(void *addr)
252 u16 val = __raw_readw(addr);
254 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);