1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
9 #include <asm/arch/immap_ls102xa.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/ls102xa_soc.h>
13 #include <asm/arch/ls102xa_devdis.h>
14 #include <asm/arch/ls102xa_sata.h>
18 #include <fsl_esdhc.h>
22 #include <fsl_devdis.h>
23 #include <fsl_validate.h>
25 #include "../common/sleep.h"
26 #include "../common/qixis.h"
27 #include "ls1021aqds_qixis.h"
32 #define PIN_MUX_SEL_CAN 0x03
33 #define PIN_MUX_SEL_IIC2 0xa0
34 #define PIN_MUX_SEL_RGMII 0x00
35 #define PIN_MUX_SEL_SAI 0x0c
36 #define PIN_MUX_SEL_SDHC 0x00
38 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
39 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
47 MUX_TYPE_SD_PC_SA_SG_SG,
48 MUX_TYPE_SD_PC_SA_PC_SG,
60 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
63 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
67 puts("Board: LS1021AQDS\n");
71 #elif CONFIG_QSPI_BOOT
74 sw = QIXIS_READ(brdcfg[0]);
75 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
78 printf("vBank: %d\n", sw);
86 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
89 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
90 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
91 QIXIS_READ(id), QIXIS_READ(arch));
93 printf("FPGA: v%d (%s), build %d\n",
94 (int)QIXIS_READ(scver), qixis_read_tag(buf),
95 (int)qixis_read_minor());
101 unsigned long get_board_sys_clk(void)
103 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
105 switch (sysclk_conf & 0x0f) {
106 case QIXIS_SYSCLK_64:
108 case QIXIS_SYSCLK_83:
110 case QIXIS_SYSCLK_100:
112 case QIXIS_SYSCLK_125:
114 case QIXIS_SYSCLK_133:
116 case QIXIS_SYSCLK_150:
118 case QIXIS_SYSCLK_160:
120 case QIXIS_SYSCLK_166:
126 unsigned long get_board_ddr_clk(void)
128 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
130 switch ((ddrclk_conf & 0x30) >> 4) {
131 case QIXIS_DDRCLK_100:
133 case QIXIS_DDRCLK_125:
135 case QIXIS_DDRCLK_133:
141 int select_i2c_ch_pca9547(u8 ch)
145 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
147 puts("PCA: failed to select proper channel\n");
157 * When resuming from deep sleep, the I2C channel may not be
158 * in the default channel. So, switch to the default channel
159 * before accessing DDR SPD.
161 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
162 return fsl_initdram();
165 #ifdef CONFIG_FSL_ESDHC
166 struct fsl_esdhc_cfg esdhc_cfg[1] = {
167 {CONFIG_SYS_FSL_ESDHC_ADDR},
170 int board_mmc_init(bd_t *bis)
172 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
174 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
178 int board_early_init_f(void)
180 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
182 #ifdef CONFIG_TSEC_ENET
183 /* clear BD & FR bits for BE BD's and frame data */
184 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
187 #ifdef CONFIG_FSL_IFC
188 init_early_memctl_regs();
193 #if defined(CONFIG_DEEP_SLEEP)
195 fsl_dp_disable_console();
201 #ifdef CONFIG_SPL_BUILD
202 void board_init_f(ulong dummy)
204 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
205 CONFIG_SYS_CCI400_OFFSET);
208 #ifdef CONFIG_NAND_BOOT
209 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
213 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
214 * NAND boot because IFC signals > IFC_AD7 are not enabled.
215 * This workaround changes RCW source to make all signals enabled.
217 porsr1 = in_be32(&gur->porsr1);
218 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
219 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
220 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
225 memset(__bss_start, 0, __bss_end - __bss_start);
227 #ifdef CONFIG_FSL_IFC
228 init_early_memctl_regs();
233 #if defined(CONFIG_DEEP_SLEEP)
235 fsl_dp_disable_console();
238 preloader_console_init();
240 #ifdef CONFIG_SPL_I2C_SUPPORT
244 major = get_soc_major_rev();
245 if (major == SOC_MAJOR_VER_1_0)
246 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
250 /* Allow OCRAM access permission as R/W */
251 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
252 enable_layerscape_ns_access();
255 board_init_r(NULL, 0);
259 void config_etseccm_source(int etsec_gtx_125_mux)
261 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
263 switch (etsec_gtx_125_mux) {
265 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
266 debug("etseccm set to GE0_CLK125\n");
270 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
271 debug("etseccm set to GE2_CLK125\n");
275 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
276 debug("etseccm set to GE1_CLK125\n");
280 printf("Error! trying to set etseccm to invalid value\n");
285 int config_board_mux(int ctrl_type)
289 reg12 = QIXIS_READ(brdcfg[12]);
290 reg14 = QIXIS_READ(brdcfg[14]);
294 config_etseccm_source(GE2_CLK125);
295 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
298 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
301 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
304 config_etseccm_source(GE2_CLK125);
305 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
308 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
310 case MUX_TYPE_SD_PCI4:
313 case MUX_TYPE_SD_PC_SA_SG_SG:
316 case MUX_TYPE_SD_PC_SA_PC_SG:
319 case MUX_TYPE_SD_PC_SG_SG:
323 printf("Wrong mux interface type\n");
327 QIXIS_WRITE(brdcfg[12], reg12);
328 QIXIS_WRITE(brdcfg[14], reg14);
333 int config_serdes_mux(void)
335 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
338 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
339 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
343 config_board_mux(MUX_TYPE_SD_PCI4);
346 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
349 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
352 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
355 printf("SRDS1 prtcl:0x%x\n", cfg);
362 #ifdef CONFIG_BOARD_LATE_INIT
363 int board_late_init(void)
365 #ifdef CONFIG_SCSI_AHCI_PLAT
368 #ifdef CONFIG_CHAIN_OF_TRUST
369 fsl_setenv_chain_of_trust();
376 int misc_init_r(void)
380 /* some signals can not enable simultaneous*/
382 if (hwconfig("sdhc"))
384 if (hwconfig("iic2"))
386 if (conflict_flag > 1) {
387 printf("WARNING: pin conflict !\n");
392 if (hwconfig("rgmii"))
398 if (conflict_flag > 1) {
399 printf("WARNING: pin conflict !\n");
404 config_board_mux(MUX_TYPE_CAN);
405 else if (hwconfig("rgmii"))
406 config_board_mux(MUX_TYPE_RGMII);
407 else if (hwconfig("sai"))
408 config_board_mux(MUX_TYPE_SAI);
410 if (hwconfig("iic2"))
411 config_board_mux(MUX_TYPE_IIC2);
412 else if (hwconfig("sdhc"))
413 config_board_mux(MUX_TYPE_SDHC);
415 #ifdef CONFIG_FSL_DEVICE_DISABLE
416 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
418 #ifdef CONFIG_FSL_CAAM
426 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
427 CONFIG_SYS_CCI400_OFFSET);
430 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
433 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
434 erratum_a009942_check_cpo();
436 major = get_soc_major_rev();
437 if (major == SOC_MAJOR_VER_1_0) {
438 /* Set CCI-400 control override register to
439 * enable barrier transaction */
440 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
443 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
445 #ifndef CONFIG_SYS_FSL_NO_SERDES
450 ls102xa_smmu_stream_id_init();
459 #if defined(CONFIG_DEEP_SLEEP)
460 void board_sleep_prepare(void)
462 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
463 CONFIG_SYS_CCI400_OFFSET);
466 major = get_soc_major_rev();
467 if (major == SOC_MAJOR_VER_1_0) {
468 /* Set CCI-400 control override register to
469 * enable barrier transaction */
470 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
474 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
475 enable_layerscape_ns_access();
480 int ft_board_setup(void *blob, bd_t *bd)
482 ft_cpu_setup(blob, bd);
485 ft_pci_setup(blob, bd);
491 u8 flash_read8(void *addr)
493 return __raw_readb(addr + 1);
496 void flash_write16(u16 val, void *addr)
498 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
500 __raw_writew(shftval, addr);
503 u16 flash_read16(void *addr)
505 u16 val = __raw_readw(addr);
507 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);