2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_devdis.h>
14 #include <asm/arch/ls102xa_soc.h>
15 #include <asm/arch/ls102xa_sata.h>
19 #include <fsl_esdhc.h>
21 #include <fsl_immap.h>
26 #include <fsl_devdis.h>
28 #include "../common/sleep.h"
32 #include <fsl_validate.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 #define VERSION_MASK 0x00FF
38 #define BANK_MASK 0x0001
39 #define CONFIG_RESET 0x1
40 #define INIT_RESET 0x1
42 #define CPLD_SET_MUX_SERDES 0x20
43 #define CPLD_SET_BOOT_BANK 0x40
45 #define BOOT_FROM_UPPER_BANK 0x0
46 #define BOOT_FROM_LOWER_BANK 0x1
48 #define LANEB_SATA (0x01)
49 #define LANEB_SGMII1 (0x02)
50 #define LANEC_SGMII1 (0x04)
51 #define LANEC_PCIEX1 (0x08)
52 #define LANED_PCIEX2 (0x10)
53 #define LANED_SGMII2 (0x20)
55 #define MASK_LANE_B 0x1
56 #define MASK_LANE_C 0x2
57 #define MASK_LANE_D 0x4
58 #define MASK_SGMII 0x8
60 #define KEEP_STATUS 0x0
61 #define NEED_RESET 0x1
63 #define SOFT_MUX_ON_I2C3_IFC 0x2
64 #define SOFT_MUX_ON_CAN3_USB2 0x8
65 #define SOFT_MUX_ON_QE_LCD 0x10
67 #define PIN_I2C3_IFC_MUX_I2C3 0x0
68 #define PIN_I2C3_IFC_MUX_IFC 0x1
69 #define PIN_CAN3_USB2_MUX_USB2 0x0
70 #define PIN_CAN3_USB2_MUX_CAN3 0x1
71 #define PIN_QE_LCD_MUX_LCD 0x0
72 #define PIN_QE_LCD_MUX_QE 0x1
75 u8 cpld_ver; /* cpld revision */
76 u8 cpld_ver_sub; /* cpld sub revision */
77 u8 pcba_ver; /* pcb revision number */
78 u8 system_rst; /* reset system by cpld */
79 u8 soft_mux_on; /* CPLD override physical switches Enable */
80 u8 cfg_rcw_src1; /* Reset config word 1 */
81 u8 cfg_rcw_src2; /* Reset config word 2 */
82 u8 vbank; /* Flash bank selection Control */
83 u8 gpio; /* GPIO for TWR-ELEV */
86 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
87 u8 qe_lcd_mux; /* QE and LCD Selection */
88 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
89 u8 global_rst; /* reset with init CPLD reg to default */
90 u8 rev1; /* Reserved */
91 u8 rev2; /* Reserved */
94 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
95 static void cpld_show(void)
97 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
99 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
100 in_8(&cpld_data->cpld_ver) & VERSION_MASK,
101 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
102 in_8(&cpld_data->pcba_ver) & VERSION_MASK,
103 in_8(&cpld_data->vbank) & BANK_MASK);
106 printf("soft_mux_on =%x\n",
107 in_8(&cpld_data->soft_mux_on));
108 printf("cfg_rcw_src1 =%x\n",
109 in_8(&cpld_data->cfg_rcw_src1));
110 printf("cfg_rcw_src2 =%x\n",
111 in_8(&cpld_data->cfg_rcw_src2));
112 printf("vbank =%x\n",
113 in_8(&cpld_data->vbank));
115 in_8(&cpld_data->gpio));
116 printf("i2c3_ifc_mux =%x\n",
117 in_8(&cpld_data->i2c3_ifc_mux));
118 printf("mux_spi2 =%x\n",
119 in_8(&cpld_data->mux_spi2));
120 printf("can3_usb2_mux =%x\n",
121 in_8(&cpld_data->can3_usb2_mux));
122 printf("qe_lcd_mux =%x\n",
123 in_8(&cpld_data->qe_lcd_mux));
124 printf("serdes_mux =%x\n",
125 in_8(&cpld_data->serdes_mux));
132 puts("Board: LS1021ATWR\n");
133 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
140 void ddrmc_init(void)
142 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
143 u32 temp_sdram_cfg, tmp;
145 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
147 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
148 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
150 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
151 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
152 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
153 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
154 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
155 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
157 #ifdef CONFIG_DEEP_SLEEP
158 if (is_warm_boot()) {
159 out_be32(&ddr->sdram_cfg_2,
160 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
161 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
162 out_be32(&ddr->init_ext_addr, (1 << 31));
164 /* DRAM VRef will not be trained */
165 out_be32(&ddr->ddr_cdr2,
166 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
170 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
171 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
174 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
175 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
177 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
179 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
181 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
182 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
184 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
186 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
187 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
189 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
191 /* DDR erratum A-009942 */
192 tmp = in_be32(&ddr->debug[28]);
193 out_be32(&ddr->debug[28], tmp | 0x0070006f);
197 #ifdef CONFIG_DEEP_SLEEP
198 if (is_warm_boot()) {
199 /* enter self-refresh */
200 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
201 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
202 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
204 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
207 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
209 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
211 #ifdef CONFIG_DEEP_SLEEP
212 if (is_warm_boot()) {
213 /* exit self-refresh */
214 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
215 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
216 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
223 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
227 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
229 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
236 #ifdef CONFIG_FSL_ESDHC
237 struct fsl_esdhc_cfg esdhc_cfg[1] = {
238 {CONFIG_SYS_FSL_ESDHC_ADDR},
241 int board_mmc_init(bd_t *bis)
243 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
245 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
249 int board_eth_init(bd_t *bis)
251 #ifdef CONFIG_TSEC_ENET
252 struct fsl_pq_mdio_info mdio_info;
253 struct tsec_info_struct tsec_info[4];
257 SET_STD_TSEC_INFO(tsec_info[num], 1);
258 if (is_serdes_configured(SGMII_TSEC1)) {
259 puts("eTSEC1 is in sgmii mode.\n");
260 tsec_info[num].flags |= TSEC_SGMII;
265 SET_STD_TSEC_INFO(tsec_info[num], 2);
266 if (is_serdes_configured(SGMII_TSEC2)) {
267 puts("eTSEC2 is in sgmii mode.\n");
268 tsec_info[num].flags |= TSEC_SGMII;
273 SET_STD_TSEC_INFO(tsec_info[num], 3);
274 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
278 printf("No TSECs initialized\n");
282 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
283 mdio_info.name = DEFAULT_MII_NAME;
284 fsl_pq_mdio_init(bis, &mdio_info);
286 tsec_eth_init(bis, tsec_info, num);
289 return pci_eth_init(bis);
292 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
293 static void convert_serdes_mux(int type, int need_reset)
296 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
298 current_serdes = cpld_data->serdes_mux;
302 current_serdes &= ~MASK_LANE_B;
305 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
308 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
311 current_serdes |= MASK_LANE_D;
314 current_serdes |= MASK_LANE_C;
316 case (LANED_PCIEX2 | LANEC_PCIEX1):
317 current_serdes |= MASK_LANE_C;
318 current_serdes &= ~MASK_LANE_D;
321 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
325 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
326 cpld_data->serdes_mux = current_serdes;
328 if (need_reset == 1) {
329 printf("Reset board to enable configuration\n");
330 cpld_data->system_rst = CONFIG_RESET;
334 int config_serdes_mux(void)
336 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
337 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
339 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
342 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
343 convert_serdes_mux(LANED_PCIEX2 |
344 LANEC_PCIEX1, KEEP_STATUS);
347 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
348 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
349 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
352 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
353 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
354 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
357 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
358 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
359 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
367 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
368 int config_board_mux(void)
370 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
374 if (hwconfig("i2c3")) {
376 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
377 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
380 if (hwconfig("ifc")) {
382 /* some signals can not enable simultaneous*/
383 if (conflict_flag > 1)
385 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
386 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
390 if (hwconfig("usb2")) {
392 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
393 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
396 if (hwconfig("can3")) {
398 /* some signals can not enable simultaneous*/
399 if (conflict_flag > 1)
401 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
402 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
406 if (hwconfig("lcd")) {
408 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
409 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
412 if (hwconfig("qe")) {
414 /* some signals can not enable simultaneous*/
415 if (conflict_flag > 1)
417 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
418 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
424 printf("WARNING: pin conflict! MUX setting may failed!\n");
429 int board_early_init_f(void)
431 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
433 #ifdef CONFIG_TSEC_ENET
434 /* clear BD & FR bits for BE BD's and frame data */
435 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
436 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
439 #ifdef CONFIG_FSL_IFC
440 init_early_memctl_regs();
445 #if defined(CONFIG_DEEP_SLEEP)
446 if (is_warm_boot()) {
455 #ifdef CONFIG_SPL_BUILD
456 void board_init_f(ulong dummy)
458 void (*second_uboot)(void);
461 memset(__bss_start, 0, __bss_end - __bss_start);
465 #if defined(CONFIG_DEEP_SLEEP)
467 fsl_dp_disable_console();
470 preloader_console_init();
474 /* Allow OCRAM access permission as R/W */
475 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
476 enable_layerscape_ns_access();
480 * if it is woken up from deep sleep, then jump to second
481 * stage uboot and continue executing without recopying
482 * it from SD since it has already been reserved in memeory
485 if (is_warm_boot()) {
486 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
490 board_init_r(NULL, 0);
494 #ifdef CONFIG_DEEP_SLEEP
495 /* program the regulator (MC34VR500) to support deep sleep */
496 void ls1twr_program_regulator(void)
498 unsigned int i2c_bus;
501 #define LS1TWR_I2C_BUS_MC34VR500 1
502 #define MC34VR500_ADDR 0x8
503 #define MC34VR500_DEVICEID 0x4
504 #define MC34VR500_DEVICEID_MASK 0x0f
506 i2c_bus = i2c_get_bus_num();
507 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
508 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
509 MC34VR500_DEVICEID_MASK;
510 if (i2c_device_id != MC34VR500_DEVICEID) {
511 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
515 i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
516 i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
517 i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
518 i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
519 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
521 i2c_set_bus_num(i2c_bus);
527 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
531 #ifndef CONFIG_SYS_FSL_NO_SERDES
533 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
538 ls102xa_smmu_stream_id_init();
544 #ifdef CONFIG_DEEP_SLEEP
545 ls1twr_program_regulator();
550 #if defined(CONFIG_SPL_BUILD)
551 void spl_board_init(void)
553 ls102xa_smmu_stream_id_init();
557 #ifdef CONFIG_BOARD_LATE_INIT
558 int board_late_init(void)
560 #ifdef CONFIG_SCSI_AHCI_PLAT
563 #ifdef CONFIG_CHAIN_OF_TRUST
564 fsl_setenv_chain_of_trust();
571 #if defined(CONFIG_MISC_INIT_R)
572 int misc_init_r(void)
574 #ifdef CONFIG_FSL_DEVICE_DISABLE
575 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
577 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
581 #ifdef CONFIG_FSL_CAAM
587 #if defined(CONFIG_DEEP_SLEEP)
588 void board_sleep_prepare(void)
590 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
591 enable_layerscape_ns_access();
596 int ft_board_setup(void *blob, bd_t *bd)
598 ft_cpu_setup(blob, bd);
601 ft_pci_setup(blob, bd);
607 u8 flash_read8(void *addr)
609 return __raw_readb(addr + 1);
612 void flash_write16(u16 val, void *addr)
614 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
616 __raw_writew(shftval, addr);
619 u16 flash_read16(void *addr)
621 u16 val = __raw_readw(addr);
623 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
626 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
627 && !defined(CONFIG_SPL_BUILD)
628 static void convert_flash_bank(char bank)
630 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
632 printf("Now switch to boot from flash bank %d.\n", bank);
633 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
634 cpld_data->vbank = bank;
636 printf("Reset board to enable configuration.\n");
637 cpld_data->system_rst = CONFIG_RESET;
640 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
644 return CMD_RET_USAGE;
645 if (strcmp(argv[1], "0") == 0)
646 convert_flash_bank(BOOT_FROM_UPPER_BANK);
647 else if (strcmp(argv[1], "1") == 0)
648 convert_flash_bank(BOOT_FROM_LOWER_BANK);
650 return CMD_RET_USAGE;
656 boot_bank, 2, 0, flash_bank_cmd,
657 "Flash bank Selection Control",
658 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
661 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
664 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
667 return CMD_RET_USAGE;
668 if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
669 cpld_data->system_rst = CONFIG_RESET;
670 else if (strcmp(argv[1], "init") == 0)
671 cpld_data->global_rst = INIT_RESET;
673 return CMD_RET_USAGE;
679 cpld_reset, 2, 0, cpld_reset_cmd,
682 " -reset with current CPLD configuration\n"
684 " -reset and initial CPLD configuration with default value"
688 static void print_serdes_mux(void)
691 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
693 current_serdes = cpld_data->serdes_mux;
695 printf("Serdes Lane B: ");
696 if ((current_serdes & MASK_LANE_B) == 0)
699 printf("SGMII 1,\n");
701 printf("Serdes Lane C: ");
702 if ((current_serdes & MASK_LANE_C) == 0)
703 printf("SGMII 1,\n");
707 printf("Serdes Lane D: ");
708 if ((current_serdes & MASK_LANE_D) == 0)
711 printf("SGMII 2,\n");
713 printf("SGMII 1 is on lane ");
714 if ((current_serdes & MASK_SGMII) == 0)
720 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
724 return CMD_RET_USAGE;
725 if (strcmp(argv[1], "sata") == 0) {
726 printf("Set serdes lane B to SATA.\n");
727 convert_serdes_mux(LANEB_SATA, NEED_RESET);
728 } else if (strcmp(argv[1], "sgmii1b") == 0) {
729 printf("Set serdes lane B to SGMII 1.\n");
730 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
731 } else if (strcmp(argv[1], "sgmii1c") == 0) {
732 printf("Set serdes lane C to SGMII 1.\n");
733 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
734 } else if (strcmp(argv[1], "sgmii2") == 0) {
735 printf("Set serdes lane D to SGMII 2.\n");
736 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
737 } else if (strcmp(argv[1], "pciex1") == 0) {
738 printf("Set serdes lane C to PCIe X1.\n");
739 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
740 } else if (strcmp(argv[1], "pciex2") == 0) {
741 printf("Set serdes lane C & lane D to PCIe X2.\n");
742 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
743 } else if (strcmp(argv[1], "show") == 0) {
746 return CMD_RET_USAGE;
753 lane_bank, 2, 0, serdes_mux_cmd,
754 "Multiplexed function setting for SerDes Lanes",
756 " -change lane B to sata\n"
757 "lane_bank sgmii1b\n"
758 " -change lane B to SGMII1\n"
759 "lane_bank sgmii1c\n"
760 " -change lane C to SGMII1\n"
762 " -change lane D to SGMII2\n"
764 " -change lane C to PCIeX1\n"
766 " -change lane C & lane D to PCIeX2\n"
767 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"