git.sur5r.net Git - u-boot/blob - board/freescale/ls1021atwr/ls1021atwr.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/ns_access.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ls102xa_stream_id.h>
  15 #include <asm/pcie_layerscape.h>
  16 #include <mmc.h>
  17 #include <fsl_esdhc.h>
  18 #include <fsl_ifc.h>
  19 #include <netdev.h>
  20 #include <fsl_mdio.h>
  21 #include <tsec.h>
  22 #include <fsl_sec.h>
  23 #include <spl.h>
  24 #ifdef CONFIG_U_QE
  25 #include "../../../drivers/qe/qe.h"
  26 #endif
  27
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define VERSION_MASK            0x00FF
  32 #define BANK_MASK               0x0001
  33 #define CONFIG_RESET            0x1
  34 #define INIT_RESET              0x1
  35
  36 #define CPLD_SET_MUX_SERDES     0x20
  37 #define CPLD_SET_BOOT_BANK      0x40
  38
  39 #define BOOT_FROM_UPPER_BANK    0x0
  40 #define BOOT_FROM_LOWER_BANK    0x1
  41
  42 #define LANEB_SATA              (0x01)
  43 #define LANEB_SGMII1            (0x02)
  44 #define LANEC_SGMII1            (0x04)
  45 #define LANEC_PCIEX1            (0x08)
  46 #define LANED_PCIEX2            (0x10)
  47 #define LANED_SGMII2            (0x20)
  48
  49 #define MASK_LANE_B             0x1
  50 #define MASK_LANE_C             0x2
  51 #define MASK_LANE_D             0x4
  52 #define MASK_SGMII              0x8
  53
  54 #define KEEP_STATUS             0x0
  55 #define NEED_RESET              0x1
  56
  57 struct cpld_data {
  58         u8 cpld_ver;            /* cpld revision */
  59         u8 cpld_ver_sub;        /* cpld sub revision */
  60         u8 pcba_ver;            /* pcb revision number */
  61         u8 system_rst;          /* reset system by cpld */
  62         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  63         u8 cfg_rcw_src1;        /* Reset config word 1 */
  64         u8 cfg_rcw_src2;        /* Reset config word 2 */
  65         u8 vbank;               /* Flash bank selection Control */
  66         u8 gpio;                /* GPIO for TWR-ELEV */
  67         u8 i2c3_ifc_mux;
  68         u8 mux_spi2;
  69         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  70         u8 qe_lcd_mux;          /* QE and LCD Selection */
  71         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  72         u8 global_rst;          /* reset with init CPLD reg to default */
  73         u8 rev1;                /* Reserved */
  74         u8 rev2;                /* Reserved */
  75 };
  76
  77 #ifndef CONFIG_QSPI_BOOT
  78 static void convert_serdes_mux(int type, int need_reset);
  79
  80 void cpld_show(void)
  81 {
  82         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  83
  84         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
  85                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
  86                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
  87                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
  88                in_8(&cpld_data->vbank) & BANK_MASK);
  89
  90 #ifdef CONFIG_DEBUG
  91         printf("soft_mux_on =%x\n",
  92                in_8(&cpld_data->soft_mux_on));
  93         printf("cfg_rcw_src1 =%x\n",
  94                in_8(&cpld_data->cfg_rcw_src1));
  95         printf("cfg_rcw_src2 =%x\n",
  96                in_8(&cpld_data->cfg_rcw_src2));
  97         printf("vbank =%x\n",
  98                in_8(&cpld_data->vbank));
  99         printf("gpio =%x\n",
 100                in_8(&cpld_data->gpio));
 101         printf("i2c3_ifc_mux =%x\n",
 102                in_8(&cpld_data->i2c3_ifc_mux));
 103         printf("mux_spi2 =%x\n",
 104                in_8(&cpld_data->mux_spi2));
 105         printf("can3_usb2_mux =%x\n",
 106                in_8(&cpld_data->can3_usb2_mux));
 107         printf("qe_lcd_mux =%x\n",
 108                in_8(&cpld_data->qe_lcd_mux));
 109         printf("serdes_mux =%x\n",
 110                in_8(&cpld_data->serdes_mux));
 111 #endif
 112 }
 113 #endif
 114
 115 int checkboard(void)
 116 {
 117         puts("Board: LS1021ATWR\n");
 118 #ifndef CONFIG_QSPI_BOOT
 119         cpld_show();
 120 #endif
 121
 122         return 0;
 123 }
 124
 125 unsigned int get_soc_major_rev(void)
 126 {
 127         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 128         unsigned int svr, major;
 129
 130         svr = in_be32(&gur->svr);
 131         major = SVR_MAJ(svr);
 132
 133         return major;
 134 }
 135
 136 void ddrmc_init(void)
 137 {
 138         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 139
 140         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 141
 142         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 143         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 144
 145         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 146         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 147         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 148         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 149         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 150         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 151
 152         out_be32(&ddr->sdram_cfg_2,  DDR_SDRAM_CFG_2);
 153
 154         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 155         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 156
 157         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 158
 159         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 160
 161         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 162         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 163
 164         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 165         out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 166
 167         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 168         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 169
 170         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 171         udelay(1);
 172         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
 173 }
 174
 175 int dram_init(void)
 176 {
 177 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 178         ddrmc_init();
 179 #endif
 180
 181         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 182         return 0;
 183 }
 184
 185 #ifdef CONFIG_FSL_ESDHC
 186 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 187         {CONFIG_SYS_FSL_ESDHC_ADDR},
 188 };
 189
 190 int board_mmc_init(bd_t *bis)
 191 {
 192         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 193
 194         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 195 }
 196 #endif
 197
 198 #ifdef CONFIG_TSEC_ENET
 199 int board_eth_init(bd_t *bis)
 200 {
 201         struct fsl_pq_mdio_info mdio_info;
 202         struct tsec_info_struct tsec_info[4];
 203         int num = 0;
 204
 205 #ifdef CONFIG_TSEC1
 206         SET_STD_TSEC_INFO(tsec_info[num], 1);
 207         if (is_serdes_configured(SGMII_TSEC1)) {
 208                 puts("eTSEC1 is in sgmii mode.\n");
 209                 tsec_info[num].flags |= TSEC_SGMII;
 210         }
 211         num++;
 212 #endif
 213 #ifdef CONFIG_TSEC2
 214         SET_STD_TSEC_INFO(tsec_info[num], 2);
 215         if (is_serdes_configured(SGMII_TSEC2)) {
 216                 puts("eTSEC2 is in sgmii mode.\n");
 217                 tsec_info[num].flags |= TSEC_SGMII;
 218         }
 219         num++;
 220 #endif
 221 #ifdef CONFIG_TSEC3
 222         SET_STD_TSEC_INFO(tsec_info[num], 3);
 223         num++;
 224 #endif
 225         if (!num) {
 226                 printf("No TSECs initialized\n");
 227                 return 0;
 228         }
 229
 230         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 231         mdio_info.name = DEFAULT_MII_NAME;
 232         fsl_pq_mdio_init(bis, &mdio_info);
 233
 234         tsec_eth_init(bis, tsec_info, num);
 235
 236         return pci_eth_init(bis);
 237 }
 238 #endif
 239
 240 #ifndef CONFIG_QSPI_BOOT
 241 int config_serdes_mux(void)
 242 {
 243         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 244         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 245
 246         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 247         switch (protocol) {
 248         case 0x10:
 249                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 250                 convert_serdes_mux(LANED_PCIEX2 |
 251                                 LANEC_PCIEX1, KEEP_STATUS);
 252                 break;
 253         case 0x20:
 254                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 255                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 256                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 257                 break;
 258         case 0x30:
 259                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 260                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 261                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 262                 break;
 263         case 0x70:
 264                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 265                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 266                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 267                 break;
 268         }
 269
 270         return 0;
 271 }
 272 #endif
 273
 274 int board_early_init_f(void)
 275 {
 276         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 277         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 278         unsigned int major;
 279
 280 #ifdef CONFIG_TSEC_ENET
 281         out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 282         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 283 #endif
 284
 285 #ifdef CONFIG_FSL_IFC
 286         init_early_memctl_regs();
 287 #endif
 288
 289 #ifdef CONFIG_FSL_DCU_FB
 290         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 291 #endif
 292
 293 #ifdef CONFIG_FSL_QSPI
 294         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 295 #endif
 296
 297         /*
 298          * Enable snoop requests and DVM message requests for
 299          * Slave insterface S4 (A7 core cluster)
 300          */
 301         out_le32(&cci->slave[4].snoop_ctrl,
 302                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 303
 304         major = get_soc_major_rev();
 305         if (major == SOC_MAJOR_VER_1_0) {
 306                 /*
 307                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 308                  * Register All transactions are treated as non-shareable
 309                  */
 310                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 311                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 312         }
 313
 314         return 0;
 315 }
 316
 317 #ifdef CONFIG_SPL_BUILD
 318 void board_init_f(ulong dummy)
 319 {
 320         /* Clear the BSS */
 321         memset(__bss_start, 0, __bss_end - __bss_start);
 322
 323         get_clocks();
 324
 325         preloader_console_init();
 326
 327         dram_init();
 328
 329         board_init_r(NULL, 0);
 330 }
 331 #endif
 332
 333 #ifdef CONFIG_LS102XA_NS_ACCESS
 334 static struct csu_ns_dev ns_dev[] = {
 335         { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
 336         { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
 337         { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
 338         { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
 339         { CSU_CSLX_OCRAM, CSU_ALL_RW },
 340         { CSU_CSLX_GIC, CSU_ALL_RW },
 341         { CSU_CSLX_PCIE1, CSU_ALL_RW },
 342         { CSU_CSLX_OCRAM2, CSU_ALL_RW },
 343         { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
 344         { CSU_CSLX_PCIE2, CSU_ALL_RW },
 345         { CSU_CSLX_SATA, CSU_ALL_RW },
 346         { CSU_CSLX_USB3, CSU_ALL_RW },
 347         { CSU_CSLX_SERDES, CSU_ALL_RW },
 348         { CSU_CSLX_QDMA, CSU_ALL_RW },
 349         { CSU_CSLX_LPUART2, CSU_ALL_RW },
 350         { CSU_CSLX_LPUART1, CSU_ALL_RW },
 351         { CSU_CSLX_LPUART4, CSU_ALL_RW },
 352         { CSU_CSLX_LPUART3, CSU_ALL_RW },
 353         { CSU_CSLX_LPUART6, CSU_ALL_RW },
 354         { CSU_CSLX_LPUART5, CSU_ALL_RW },
 355         { CSU_CSLX_DSPI2, CSU_ALL_RW },
 356         { CSU_CSLX_DSPI1, CSU_ALL_RW },
 357         { CSU_CSLX_QSPI, CSU_ALL_RW },
 358         { CSU_CSLX_ESDHC, CSU_ALL_RW },
 359         { CSU_CSLX_2D_ACE, CSU_ALL_RW },
 360         { CSU_CSLX_IFC, CSU_ALL_RW },
 361         { CSU_CSLX_I2C1, CSU_ALL_RW },
 362         { CSU_CSLX_USB2, CSU_ALL_RW },
 363         { CSU_CSLX_I2C3, CSU_ALL_RW },
 364         { CSU_CSLX_I2C2, CSU_ALL_RW },
 365         { CSU_CSLX_DUART2, CSU_ALL_RW },
 366         { CSU_CSLX_DUART1, CSU_ALL_RW },
 367         { CSU_CSLX_WDT2, CSU_ALL_RW },
 368         { CSU_CSLX_WDT1, CSU_ALL_RW },
 369         { CSU_CSLX_EDMA, CSU_ALL_RW },
 370         { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
 371         { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
 372         { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
 373         { CSU_CSLX_DDR, CSU_ALL_RW },
 374         { CSU_CSLX_QUICC, CSU_ALL_RW },
 375         { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
 376         { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
 377         { CSU_CSLX_SFP, CSU_ALL_RW },
 378         { CSU_CSLX_TMU, CSU_ALL_RW },
 379         { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
 380         { CSU_CSLX_RESERVED0, CSU_ALL_RW },
 381         { CSU_CSLX_ETSEC1, CSU_ALL_RW },
 382         { CSU_CSLX_SEC5_5, CSU_ALL_RW },
 383         { CSU_CSLX_ETSEC3, CSU_ALL_RW },
 384         { CSU_CSLX_ETSEC2, CSU_ALL_RW },
 385         { CSU_CSLX_GPIO2, CSU_ALL_RW },
 386         { CSU_CSLX_GPIO1, CSU_ALL_RW },
 387         { CSU_CSLX_GPIO4, CSU_ALL_RW },
 388         { CSU_CSLX_GPIO3, CSU_ALL_RW },
 389         { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
 390         { CSU_CSLX_CSU, CSU_ALL_RW },
 391         { CSU_CSLX_ASRC, CSU_ALL_RW },
 392         { CSU_CSLX_SPDIF, CSU_ALL_RW },
 393         { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
 394         { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
 395         { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
 396         { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
 397         { CSU_CSLX_SAI2, CSU_ALL_RW },
 398         { CSU_CSLX_SAI1, CSU_ALL_RW },
 399         { CSU_CSLX_SAI4, CSU_ALL_RW },
 400         { CSU_CSLX_SAI3, CSU_ALL_RW },
 401         { CSU_CSLX_FTM2, CSU_ALL_RW },
 402         { CSU_CSLX_FTM1, CSU_ALL_RW },
 403         { CSU_CSLX_FTM4, CSU_ALL_RW },
 404         { CSU_CSLX_FTM3, CSU_ALL_RW },
 405         { CSU_CSLX_FTM6, CSU_ALL_RW },
 406         { CSU_CSLX_FTM5, CSU_ALL_RW },
 407         { CSU_CSLX_FTM8, CSU_ALL_RW },
 408         { CSU_CSLX_FTM7, CSU_ALL_RW },
 409         { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
 410         { CSU_CSLX_EPU, CSU_ALL_RW },
 411         { CSU_CSLX_GDI, CSU_ALL_RW },
 412         { CSU_CSLX_DDI, CSU_ALL_RW },
 413         { CSU_CSLX_RESERVED1, CSU_ALL_RW },
 414         { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
 415         { CSU_CSLX_RESERVED2, CSU_ALL_RW },
 416 };
 417 #endif
 418
 419 struct liodn_id_table sec_liodn_tbl[] = {
 420         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
 421         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
 422         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
 423         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
 424         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
 425         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
 426         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
 427         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
 428         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
 429         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
 430         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
 431         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
 432         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
 433         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
 434         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
 435         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
 436 };
 437
 438 struct smmu_stream_id dev_stream_id[] = {
 439         { 0x100, 0x01, "ETSEC MAC1" },
 440         { 0x104, 0x02, "ETSEC MAC2" },
 441         { 0x108, 0x03, "ETSEC MAC3" },
 442         { 0x10c, 0x04, "PEX1" },
 443         { 0x110, 0x05, "PEX2" },
 444         { 0x114, 0x06, "qDMA" },
 445         { 0x118, 0x07, "SATA" },
 446         { 0x11c, 0x08, "USB3" },
 447         { 0x120, 0x09, "QE" },
 448         { 0x124, 0x0a, "eSDHC" },
 449         { 0x128, 0x0b, "eMA" },
 450         { 0x14c, 0x0c, "2D-ACE" },
 451         { 0x150, 0x0d, "USB2" },
 452         { 0x18c, 0x0e, "DEBUG" },
 453 };
 454
 455 int board_init(void)
 456 {
 457 #ifndef CONFIG_SYS_FSL_NO_SERDES
 458         fsl_serdes_init();
 459 #ifndef CONFIG_QSPI_BOOT
 460         config_serdes_mux();
 461 #endif
 462 #endif
 463
 464         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 465                                       ARRAY_SIZE(sec_liodn_tbl));
 466         ls102xa_config_smmu_stream_id(dev_stream_id,
 467                                       ARRAY_SIZE(dev_stream_id));
 468
 469 #ifdef CONFIG_LS102XA_NS_ACCESS
 470         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 471 #endif
 472
 473 #ifdef CONFIG_U_QE
 474         u_qe_init();
 475 #endif
 476
 477         return 0;
 478 }
 479
 480 #if defined(CONFIG_MISC_INIT_R)
 481 int misc_init_r(void)
 482 {
 483 #ifdef CONFIG_FSL_CAAM
 484         return sec_init();
 485 #endif
 486 }
 487 #endif
 488
 489 int ft_board_setup(void *blob, bd_t *bd)
 490 {
 491         ft_cpu_setup(blob, bd);
 492
 493 #ifdef CONFIG_PCIE_LAYERSCAPE
 494         ft_pcie_setup(blob, bd);
 495 #endif
 496
 497         return 0;
 498 }
 499
 500 u8 flash_read8(void *addr)
 501 {
 502         return __raw_readb(addr + 1);
 503 }
 504
 505 void flash_write16(u16 val, void *addr)
 506 {
 507         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 508
 509         __raw_writew(shftval, addr);
 510 }
 511
 512 u16 flash_read16(void *addr)
 513 {
 514         u16 val = __raw_readw(addr);
 515
 516         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 517 }
 518
 519 #ifndef CONFIG_QSPI_BOOT
 520 static void convert_flash_bank(char bank)
 521 {
 522         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 523
 524         printf("Now switch to boot from flash bank %d.\n", bank);
 525         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 526         cpld_data->vbank = bank;
 527
 528         printf("Reset board to enable configuration.\n");
 529         cpld_data->system_rst = CONFIG_RESET;
 530 }
 531
 532 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 533                           char * const argv[])
 534 {
 535         if (argc != 2)
 536                 return CMD_RET_USAGE;
 537         if (strcmp(argv[1], "0") == 0)
 538                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 539         else if (strcmp(argv[1], "1") == 0)
 540                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 541         else
 542                 return CMD_RET_USAGE;
 543
 544         return 0;
 545 }
 546
 547 U_BOOT_CMD(
 548         boot_bank, 2, 0, flash_bank_cmd,
 549         "Flash bank Selection Control",
 550         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 551 );
 552
 553 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 554                           char * const argv[])
 555 {
 556         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 557
 558         if (argc > 2)
 559                 return CMD_RET_USAGE;
 560         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 561                 cpld_data->system_rst = CONFIG_RESET;
 562         else if (strcmp(argv[1], "init") == 0)
 563                 cpld_data->global_rst = INIT_RESET;
 564         else
 565                 return CMD_RET_USAGE;
 566
 567         return 0;
 568 }
 569
 570 U_BOOT_CMD(
 571         cpld_reset, 2, 0, cpld_reset_cmd,
 572         "Reset via CPLD",
 573         "conf\n"
 574         "       -reset with current CPLD configuration\n"
 575         "init\n"
 576         "       -reset and initial CPLD configuration with default value"
 577
 578 );
 579
 580 static void convert_serdes_mux(int type, int need_reset)
 581 {
 582         char current_serdes;
 583         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 584
 585         current_serdes = cpld_data->serdes_mux;
 586
 587         switch (type) {
 588         case LANEB_SATA:
 589                 current_serdes &= ~MASK_LANE_B;
 590                 break;
 591         case LANEB_SGMII1:
 592                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 593                 break;
 594         case LANEC_SGMII1:
 595                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 596                 break;
 597         case LANED_SGMII2:
 598                 current_serdes |= MASK_LANE_D;
 599                 break;
 600         case LANEC_PCIEX1:
 601                 current_serdes |= MASK_LANE_C;
 602                 break;
 603         case (LANED_PCIEX2 | LANEC_PCIEX1):
 604                 current_serdes |= MASK_LANE_C;
 605                 current_serdes &= ~MASK_LANE_D;
 606                 break;
 607         default:
 608                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 609                 return;
 610         }
 611
 612         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 613         cpld_data->serdes_mux = current_serdes;
 614
 615         if (need_reset == 1) {
 616                 printf("Reset board to enable configuration\n");
 617                 cpld_data->system_rst = CONFIG_RESET;
 618         }
 619 }
 620
 621 void print_serdes_mux(void)
 622 {
 623         char current_serdes;
 624         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 625
 626         current_serdes = cpld_data->serdes_mux;
 627
 628         printf("Serdes Lane B: ");
 629         if ((current_serdes & MASK_LANE_B) == 0)
 630                 printf("SATA,\n");
 631         else
 632                 printf("SGMII 1,\n");
 633
 634         printf("Serdes Lane C: ");
 635         if ((current_serdes & MASK_LANE_C) == 0)
 636                 printf("SGMII 1,\n");
 637         else
 638                 printf("PCIe,\n");
 639
 640         printf("Serdes Lane D: ");
 641         if ((current_serdes & MASK_LANE_D) == 0)
 642                 printf("PCIe,\n");
 643         else
 644                 printf("SGMII 2,\n");
 645
 646         printf("SGMII 1 is on lane ");
 647         if ((current_serdes & MASK_SGMII) == 0)
 648                 printf("C.\n");
 649         else
 650                 printf("B.\n");
 651 }
 652
 653 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 654                           char * const argv[])
 655 {
 656         if (argc != 2)
 657                 return CMD_RET_USAGE;
 658         if (strcmp(argv[1], "sata") == 0) {
 659                 printf("Set serdes lane B to SATA.\n");
 660                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 661         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 662                 printf("Set serdes lane B to SGMII 1.\n");
 663                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 664         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 665                 printf("Set serdes lane C to SGMII 1.\n");
 666                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 667         } else if (strcmp(argv[1], "sgmii2") == 0) {
 668                 printf("Set serdes lane D to SGMII 2.\n");
 669                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 670         } else if (strcmp(argv[1], "pciex1") == 0) {
 671                 printf("Set serdes lane C to PCIe X1.\n");
 672                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 673         } else if (strcmp(argv[1], "pciex2") == 0) {
 674                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 675                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 676         } else if (strcmp(argv[1], "show") == 0) {
 677                 print_serdes_mux();
 678         } else {
 679                 return CMD_RET_USAGE;
 680         }
 681
 682         return 0;
 683 }
 684
 685 U_BOOT_CMD(
 686         lane_bank, 2, 0, serdes_mux_cmd,
 687         "Multiplexed function setting for SerDes Lanes",
 688         "sata\n"
 689         "       -change lane B to sata\n"
 690         "lane_bank sgmii1b\n"
 691         "       -change lane B to SGMII1\n"
 692         "lane_bank sgmii1c\n"
 693         "       -change lane C to SGMII1\n"
 694         "lane_bank sgmii2\n"
 695         "       -change lane D to SGMII2\n"
 696         "lane_bank pciex1\n"
 697         "       -change lane C to PCIeX1\n"
 698         "lane_bank pciex2\n"
 699         "       -change lane C & lane D to PCIeX2\n"
 700         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 701 );
 702 #endif