git.sur5r.net Git - u-boot/blob - board/freescale/ls1021atwr/ls1021atwr.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/ls102xa_stream_id.h>
  14 #include <asm/arch/ls102xa_devdis.h>
  15 #include <asm/arch/ls102xa_soc.h>
  16 #include <asm/arch/ls102xa_sata.h>
  17 #include <hwconfig.h>
  18 #include <mmc.h>
  19 #include <fsl_csu.h>
  20 #include <fsl_esdhc.h>
  21 #include <fsl_ifc.h>
  22 #include <fsl_immap.h>
  23 #include <netdev.h>
  24 #include <fsl_mdio.h>
  25 #include <tsec.h>
  26 #include <fsl_sec.h>
  27 #include <fsl_devdis.h>
  28 #include <spl.h>
  29 #include "../common/sleep.h"
  30 #ifdef CONFIG_U_QE
  31 #include "../../../drivers/qe/qe.h"
  32 #endif
  33
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #define VERSION_MASK            0x00FF
  38 #define BANK_MASK               0x0001
  39 #define CONFIG_RESET            0x1
  40 #define INIT_RESET              0x1
  41
  42 #define CPLD_SET_MUX_SERDES     0x20
  43 #define CPLD_SET_BOOT_BANK      0x40
  44
  45 #define BOOT_FROM_UPPER_BANK    0x0
  46 #define BOOT_FROM_LOWER_BANK    0x1
  47
  48 #define LANEB_SATA              (0x01)
  49 #define LANEB_SGMII1            (0x02)
  50 #define LANEC_SGMII1            (0x04)
  51 #define LANEC_PCIEX1            (0x08)
  52 #define LANED_PCIEX2            (0x10)
  53 #define LANED_SGMII2            (0x20)
  54
  55 #define MASK_LANE_B             0x1
  56 #define MASK_LANE_C             0x2
  57 #define MASK_LANE_D             0x4
  58 #define MASK_SGMII              0x8
  59
  60 #define KEEP_STATUS             0x0
  61 #define NEED_RESET              0x1
  62
  63 #define SOFT_MUX_ON_I2C3_IFC    0x2
  64 #define SOFT_MUX_ON_CAN3_USB2   0x8
  65 #define SOFT_MUX_ON_QE_LCD      0x10
  66
  67 #define PIN_I2C3_IFC_MUX_I2C3   0x0
  68 #define PIN_I2C3_IFC_MUX_IFC    0x1
  69 #define PIN_CAN3_USB2_MUX_USB2  0x0
  70 #define PIN_CAN3_USB2_MUX_CAN3  0x1
  71 #define PIN_QE_LCD_MUX_LCD      0x0
  72 #define PIN_QE_LCD_MUX_QE       0x1
  73
  74 struct cpld_data {
  75         u8 cpld_ver;            /* cpld revision */
  76         u8 cpld_ver_sub;        /* cpld sub revision */
  77         u8 pcba_ver;            /* pcb revision number */
  78         u8 system_rst;          /* reset system by cpld */
  79         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  80         u8 cfg_rcw_src1;        /* Reset config word 1 */
  81         u8 cfg_rcw_src2;        /* Reset config word 2 */
  82         u8 vbank;               /* Flash bank selection Control */
  83         u8 gpio;                /* GPIO for TWR-ELEV */
  84         u8 i2c3_ifc_mux;
  85         u8 mux_spi2;
  86         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  87         u8 qe_lcd_mux;          /* QE and LCD Selection */
  88         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  89         u8 global_rst;          /* reset with init CPLD reg to default */
  90         u8 rev1;                /* Reserved */
  91         u8 rev2;                /* Reserved */
  92 };
  93
  94 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  95 static void convert_serdes_mux(int type, int need_reset);
  96
  97 void cpld_show(void)
  98 {
  99         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 100
 101         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
 102                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
 103                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
 104                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
 105                in_8(&cpld_data->vbank) & BANK_MASK);
 106
 107 #ifdef CONFIG_DEBUG
 108         printf("soft_mux_on =%x\n",
 109                in_8(&cpld_data->soft_mux_on));
 110         printf("cfg_rcw_src1 =%x\n",
 111                in_8(&cpld_data->cfg_rcw_src1));
 112         printf("cfg_rcw_src2 =%x\n",
 113                in_8(&cpld_data->cfg_rcw_src2));
 114         printf("vbank =%x\n",
 115                in_8(&cpld_data->vbank));
 116         printf("gpio =%x\n",
 117                in_8(&cpld_data->gpio));
 118         printf("i2c3_ifc_mux =%x\n",
 119                in_8(&cpld_data->i2c3_ifc_mux));
 120         printf("mux_spi2 =%x\n",
 121                in_8(&cpld_data->mux_spi2));
 122         printf("can3_usb2_mux =%x\n",
 123                in_8(&cpld_data->can3_usb2_mux));
 124         printf("qe_lcd_mux =%x\n",
 125                in_8(&cpld_data->qe_lcd_mux));
 126         printf("serdes_mux =%x\n",
 127                in_8(&cpld_data->serdes_mux));
 128 #endif
 129 }
 130 #endif
 131
 132 int checkboard(void)
 133 {
 134         puts("Board: LS1021ATWR\n");
 135 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 136         cpld_show();
 137 #endif
 138
 139         return 0;
 140 }
 141
 142 void ddrmc_init(void)
 143 {
 144         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 145         u32 temp_sdram_cfg;
 146
 147         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 148
 149         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 150         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 151
 152         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 153         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 154         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 155         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 156         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 157         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 158
 159 #ifdef CONFIG_DEEP_SLEEP
 160         if (is_warm_boot()) {
 161                 out_be32(&ddr->sdram_cfg_2,
 162                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
 163                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 164                 out_be32(&ddr->init_ext_addr, (1 << 31));
 165
 166                 /* DRAM VRef will not be trained */
 167                 out_be32(&ddr->ddr_cdr2,
 168                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
 169         } else
 170 #endif
 171         {
 172                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
 173                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 174         }
 175
 176         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 177         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 178
 179         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 180
 181         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 182
 183         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 184         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 185
 186         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 187
 188         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 189         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 190
 191         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 192         udelay(1);
 193
 194 #ifdef CONFIG_DEEP_SLEEP
 195         if (is_warm_boot()) {
 196                 /* enter self-refresh */
 197                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 198                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 199                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 200
 201                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
 202         } else
 203 #endif
 204                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
 205
 206         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
 207
 208 #ifdef CONFIG_DEEP_SLEEP
 209         if (is_warm_boot()) {
 210                 /* exit self-refresh */
 211                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 212                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 213                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 214         }
 215 #endif
 216 }
 217
 218 int dram_init(void)
 219 {
 220 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 221         ddrmc_init();
 222 #endif
 223
 224         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 225
 226 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 227         fsl_dp_resume();
 228 #endif
 229
 230         return 0;
 231 }
 232
 233 #ifdef CONFIG_FSL_ESDHC
 234 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 235         {CONFIG_SYS_FSL_ESDHC_ADDR},
 236 };
 237
 238 int board_mmc_init(bd_t *bis)
 239 {
 240         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 241
 242         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 243 }
 244 #endif
 245
 246 #ifdef CONFIG_TSEC_ENET
 247 int board_eth_init(bd_t *bis)
 248 {
 249         struct fsl_pq_mdio_info mdio_info;
 250         struct tsec_info_struct tsec_info[4];
 251         int num = 0;
 252
 253 #ifdef CONFIG_TSEC1
 254         SET_STD_TSEC_INFO(tsec_info[num], 1);
 255         if (is_serdes_configured(SGMII_TSEC1)) {
 256                 puts("eTSEC1 is in sgmii mode.\n");
 257                 tsec_info[num].flags |= TSEC_SGMII;
 258         }
 259         num++;
 260 #endif
 261 #ifdef CONFIG_TSEC2
 262         SET_STD_TSEC_INFO(tsec_info[num], 2);
 263         if (is_serdes_configured(SGMII_TSEC2)) {
 264                 puts("eTSEC2 is in sgmii mode.\n");
 265                 tsec_info[num].flags |= TSEC_SGMII;
 266         }
 267         num++;
 268 #endif
 269 #ifdef CONFIG_TSEC3
 270         SET_STD_TSEC_INFO(tsec_info[num], 3);
 271         num++;
 272 #endif
 273         if (!num) {
 274                 printf("No TSECs initialized\n");
 275                 return 0;
 276         }
 277
 278         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 279         mdio_info.name = DEFAULT_MII_NAME;
 280         fsl_pq_mdio_init(bis, &mdio_info);
 281
 282         tsec_eth_init(bis, tsec_info, num);
 283
 284         return pci_eth_init(bis);
 285 }
 286 #endif
 287
 288 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 289 int config_serdes_mux(void)
 290 {
 291         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 292         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 293
 294         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 295         switch (protocol) {
 296         case 0x10:
 297                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 298                 convert_serdes_mux(LANED_PCIEX2 |
 299                                 LANEC_PCIEX1, KEEP_STATUS);
 300                 break;
 301         case 0x20:
 302                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 303                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 304                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 305                 break;
 306         case 0x30:
 307                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 308                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 309                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 310                 break;
 311         case 0x70:
 312                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 313                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 314                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 315                 break;
 316         }
 317
 318         return 0;
 319 }
 320 #endif
 321
 322 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 323 int config_board_mux(void)
 324 {
 325         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 326         int conflict_flag;
 327
 328         conflict_flag = 0;
 329         if (hwconfig("i2c3")) {
 330                 conflict_flag++;
 331                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 332                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
 333         }
 334
 335         if (hwconfig("ifc")) {
 336                 conflict_flag++;
 337                 /* some signals can not enable simultaneous*/
 338                 if (conflict_flag > 1)
 339                         goto conflict;
 340                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 341                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
 342         }
 343
 344         conflict_flag = 0;
 345         if (hwconfig("usb2")) {
 346                 conflict_flag++;
 347                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 348                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
 349         }
 350
 351         if (hwconfig("can3")) {
 352                 conflict_flag++;
 353                 /* some signals can not enable simultaneous*/
 354                 if (conflict_flag > 1)
 355                         goto conflict;
 356                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 357                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
 358         }
 359
 360         conflict_flag = 0;
 361         if (hwconfig("lcd")) {
 362                 conflict_flag++;
 363                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 364                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
 365         }
 366
 367         if (hwconfig("qe")) {
 368                 conflict_flag++;
 369                 /* some signals can not enable simultaneous*/
 370                 if (conflict_flag > 1)
 371                         goto conflict;
 372                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 373                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
 374         }
 375
 376         return 0;
 377
 378 conflict:
 379         printf("WARNING: pin conflict! MUX setting may failed!\n");
 380         return 0;
 381 }
 382 #endif
 383
 384 int board_early_init_f(void)
 385 {
 386         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 387
 388 #ifdef CONFIG_TSEC_ENET
 389         /* clear BD & FR bits for BE BD's and frame data */
 390         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 391         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 392 #endif
 393
 394 #ifdef CONFIG_FSL_IFC
 395         init_early_memctl_regs();
 396 #endif
 397
 398         arch_soc_init();
 399
 400 #if defined(CONFIG_DEEP_SLEEP)
 401         if (is_warm_boot()) {
 402                 timer_init();
 403                 dram_init();
 404         }
 405 #endif
 406
 407         return 0;
 408 }
 409
 410 #ifdef CONFIG_SPL_BUILD
 411 void board_init_f(ulong dummy)
 412 {
 413         void (*second_uboot)(void);
 414
 415         /* Clear the BSS */
 416         memset(__bss_start, 0, __bss_end - __bss_start);
 417
 418         get_clocks();
 419
 420 #if defined(CONFIG_DEEP_SLEEP)
 421         if (is_warm_boot())
 422                 fsl_dp_disable_console();
 423 #endif
 424
 425         preloader_console_init();
 426
 427         dram_init();
 428
 429         /* Allow OCRAM access permission as R/W */
 430 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 431         enable_layerscape_ns_access();
 432         enable_layerscape_ns_access();
 433 #endif
 434
 435         /*
 436          * if it is woken up from deep sleep, then jump to second
 437          * stage uboot and continue executing without recopying
 438          * it from SD since it has already been reserved in memeory
 439          * in last boot.
 440          */
 441         if (is_warm_boot()) {
 442                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
 443                 second_uboot();
 444         }
 445
 446         board_init_r(NULL, 0);
 447 }
 448 #endif
 449
 450
 451 struct liodn_id_table sec_liodn_tbl[] = {
 452         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
 453         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
 454         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
 455         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
 456         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
 457         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
 458         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
 459         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
 460         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
 461         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
 462         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
 463         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
 464         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
 465         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
 466         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
 467         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
 468 };
 469
 470 struct smmu_stream_id dev_stream_id[] = {
 471         { 0x100, 0x01, "ETSEC MAC1" },
 472         { 0x104, 0x02, "ETSEC MAC2" },
 473         { 0x108, 0x03, "ETSEC MAC3" },
 474         { 0x10c, 0x04, "PEX1" },
 475         { 0x110, 0x05, "PEX2" },
 476         { 0x114, 0x06, "qDMA" },
 477         { 0x118, 0x07, "SATA" },
 478         { 0x11c, 0x08, "USB3" },
 479         { 0x120, 0x09, "QE" },
 480         { 0x124, 0x0a, "eSDHC" },
 481         { 0x128, 0x0b, "eMA" },
 482         { 0x14c, 0x0c, "2D-ACE" },
 483         { 0x150, 0x0d, "USB2" },
 484         { 0x18c, 0x0e, "DEBUG" },
 485 };
 486
 487 #ifdef CONFIG_DEEP_SLEEP
 488 /* program the regulator (MC34VR500) to support deep sleep */
 489 void ls1twr_program_regulator(void)
 490 {
 491         unsigned int i2c_bus;
 492         u8 i2c_device_id;
 493
 494 #define LS1TWR_I2C_BUS_MC34VR500        1
 495 #define MC34VR500_ADDR                  0x8
 496 #define MC34VR500_DEVICEID              0x4
 497 #define MC34VR500_DEVICEID_MASK         0x0f
 498
 499         i2c_bus = i2c_get_bus_num();
 500         i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
 501         i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
 502                                         MC34VR500_DEVICEID_MASK;
 503         if (i2c_device_id != MC34VR500_DEVICEID) {
 504                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 505                 return;
 506         }
 507
 508         i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
 509         i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
 510         i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
 511         i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
 512         i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
 513
 514         i2c_set_bus_num(i2c_bus);
 515 }
 516 #endif
 517
 518 int board_init(void)
 519 {
 520 #ifndef CONFIG_SYS_FSL_NO_SERDES
 521         fsl_serdes_init();
 522 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 523         config_serdes_mux();
 524 #endif
 525 #endif
 526
 527         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 528                                       ARRAY_SIZE(sec_liodn_tbl));
 529         ls102xa_config_smmu_stream_id(dev_stream_id,
 530                                       ARRAY_SIZE(dev_stream_id));
 531
 532 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 533         enable_layerscape_ns_access();
 534 #endif
 535
 536 #ifdef CONFIG_U_QE
 537         u_qe_init();
 538 #endif
 539
 540 #ifdef CONFIG_DEEP_SLEEP
 541         ls1twr_program_regulator();
 542 #endif
 543         return 0;
 544 }
 545
 546 #ifdef CONFIG_BOARD_LATE_INIT
 547 int board_late_init(void)
 548 {
 549 #ifdef CONFIG_SCSI_AHCI_PLAT
 550         ls1021a_sata_init();
 551 #endif
 552
 553         return 0;
 554 }
 555 #endif
 556
 557 #if defined(CONFIG_MISC_INIT_R)
 558 int misc_init_r(void)
 559 {
 560 #ifdef CONFIG_FSL_DEVICE_DISABLE
 561         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 562 #endif
 563 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 564         config_board_mux();
 565 #endif
 566
 567 #ifdef CONFIG_FSL_CAAM
 568         return sec_init();
 569 #endif
 570 }
 571 #endif
 572
 573 #if defined(CONFIG_DEEP_SLEEP)
 574 void board_sleep_prepare(void)
 575 {
 576 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 577         enable_layerscape_ns_access();
 578 #endif
 579 }
 580 #endif
 581
 582 int ft_board_setup(void *blob, bd_t *bd)
 583 {
 584         ft_cpu_setup(blob, bd);
 585
 586 #ifdef CONFIG_PCI
 587         ft_pci_setup(blob, bd);
 588 #endif
 589
 590         return 0;
 591 }
 592
 593 u8 flash_read8(void *addr)
 594 {
 595         return __raw_readb(addr + 1);
 596 }
 597
 598 void flash_write16(u16 val, void *addr)
 599 {
 600         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 601
 602         __raw_writew(shftval, addr);
 603 }
 604
 605 u16 flash_read16(void *addr)
 606 {
 607         u16 val = __raw_readw(addr);
 608
 609         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 610 }
 611
 612 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 613 static void convert_flash_bank(char bank)
 614 {
 615         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 616
 617         printf("Now switch to boot from flash bank %d.\n", bank);
 618         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 619         cpld_data->vbank = bank;
 620
 621         printf("Reset board to enable configuration.\n");
 622         cpld_data->system_rst = CONFIG_RESET;
 623 }
 624
 625 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 626                           char * const argv[])
 627 {
 628         if (argc != 2)
 629                 return CMD_RET_USAGE;
 630         if (strcmp(argv[1], "0") == 0)
 631                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 632         else if (strcmp(argv[1], "1") == 0)
 633                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 634         else
 635                 return CMD_RET_USAGE;
 636
 637         return 0;
 638 }
 639
 640 U_BOOT_CMD(
 641         boot_bank, 2, 0, flash_bank_cmd,
 642         "Flash bank Selection Control",
 643         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 644 );
 645
 646 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 647                           char * const argv[])
 648 {
 649         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 650
 651         if (argc > 2)
 652                 return CMD_RET_USAGE;
 653         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 654                 cpld_data->system_rst = CONFIG_RESET;
 655         else if (strcmp(argv[1], "init") == 0)
 656                 cpld_data->global_rst = INIT_RESET;
 657         else
 658                 return CMD_RET_USAGE;
 659
 660         return 0;
 661 }
 662
 663 U_BOOT_CMD(
 664         cpld_reset, 2, 0, cpld_reset_cmd,
 665         "Reset via CPLD",
 666         "conf\n"
 667         "       -reset with current CPLD configuration\n"
 668         "init\n"
 669         "       -reset and initial CPLD configuration with default value"
 670
 671 );
 672
 673 static void convert_serdes_mux(int type, int need_reset)
 674 {
 675         char current_serdes;
 676         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 677
 678         current_serdes = cpld_data->serdes_mux;
 679
 680         switch (type) {
 681         case LANEB_SATA:
 682                 current_serdes &= ~MASK_LANE_B;
 683                 break;
 684         case LANEB_SGMII1:
 685                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 686                 break;
 687         case LANEC_SGMII1:
 688                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 689                 break;
 690         case LANED_SGMII2:
 691                 current_serdes |= MASK_LANE_D;
 692                 break;
 693         case LANEC_PCIEX1:
 694                 current_serdes |= MASK_LANE_C;
 695                 break;
 696         case (LANED_PCIEX2 | LANEC_PCIEX1):
 697                 current_serdes |= MASK_LANE_C;
 698                 current_serdes &= ~MASK_LANE_D;
 699                 break;
 700         default:
 701                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 702                 return;
 703         }
 704
 705         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 706         cpld_data->serdes_mux = current_serdes;
 707
 708         if (need_reset == 1) {
 709                 printf("Reset board to enable configuration\n");
 710                 cpld_data->system_rst = CONFIG_RESET;
 711         }
 712 }
 713
 714 void print_serdes_mux(void)
 715 {
 716         char current_serdes;
 717         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 718
 719         current_serdes = cpld_data->serdes_mux;
 720
 721         printf("Serdes Lane B: ");
 722         if ((current_serdes & MASK_LANE_B) == 0)
 723                 printf("SATA,\n");
 724         else
 725                 printf("SGMII 1,\n");
 726
 727         printf("Serdes Lane C: ");
 728         if ((current_serdes & MASK_LANE_C) == 0)
 729                 printf("SGMII 1,\n");
 730         else
 731                 printf("PCIe,\n");
 732
 733         printf("Serdes Lane D: ");
 734         if ((current_serdes & MASK_LANE_D) == 0)
 735                 printf("PCIe,\n");
 736         else
 737                 printf("SGMII 2,\n");
 738
 739         printf("SGMII 1 is on lane ");
 740         if ((current_serdes & MASK_SGMII) == 0)
 741                 printf("C.\n");
 742         else
 743                 printf("B.\n");
 744 }
 745
 746 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 747                           char * const argv[])
 748 {
 749         if (argc != 2)
 750                 return CMD_RET_USAGE;
 751         if (strcmp(argv[1], "sata") == 0) {
 752                 printf("Set serdes lane B to SATA.\n");
 753                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 754         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 755                 printf("Set serdes lane B to SGMII 1.\n");
 756                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 757         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 758                 printf("Set serdes lane C to SGMII 1.\n");
 759                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 760         } else if (strcmp(argv[1], "sgmii2") == 0) {
 761                 printf("Set serdes lane D to SGMII 2.\n");
 762                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 763         } else if (strcmp(argv[1], "pciex1") == 0) {
 764                 printf("Set serdes lane C to PCIe X1.\n");
 765                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 766         } else if (strcmp(argv[1], "pciex2") == 0) {
 767                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 768                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 769         } else if (strcmp(argv[1], "show") == 0) {
 770                 print_serdes_mux();
 771         } else {
 772                 return CMD_RET_USAGE;
 773         }
 774
 775         return 0;
 776 }
 777
 778 U_BOOT_CMD(
 779         lane_bank, 2, 0, serdes_mux_cmd,
 780         "Multiplexed function setting for SerDes Lanes",
 781         "sata\n"
 782         "       -change lane B to sata\n"
 783         "lane_bank sgmii1b\n"
 784         "       -change lane B to SGMII1\n"
 785         "lane_bank sgmii1c\n"
 786         "       -change lane C to SGMII1\n"
 787         "lane_bank sgmii2\n"
 788         "       -change lane D to SGMII2\n"
 789         "lane_bank pciex1\n"
 790         "       -change lane C to PCIeX1\n"
 791         "lane_bank pciex2\n"
 792         "       -change lane C & lane D to PCIeX2\n"
 793         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 794 );
 795 #endif