2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ls102xa_stream_id.h>
14 #include <asm/arch/ls102xa_devdis.h>
15 #include <asm/arch/ls102xa_sata.h>
19 #include <fsl_esdhc.h>
21 #include <fsl_immap.h>
26 #include <fsl_devdis.h>
28 #include "../common/sleep.h"
30 #include "../../../drivers/qe/qe.h"
34 DECLARE_GLOBAL_DATA_PTR;
36 #define VERSION_MASK 0x00FF
37 #define BANK_MASK 0x0001
38 #define CONFIG_RESET 0x1
39 #define INIT_RESET 0x1
41 #define CPLD_SET_MUX_SERDES 0x20
42 #define CPLD_SET_BOOT_BANK 0x40
44 #define BOOT_FROM_UPPER_BANK 0x0
45 #define BOOT_FROM_LOWER_BANK 0x1
47 #define LANEB_SATA (0x01)
48 #define LANEB_SGMII1 (0x02)
49 #define LANEC_SGMII1 (0x04)
50 #define LANEC_PCIEX1 (0x08)
51 #define LANED_PCIEX2 (0x10)
52 #define LANED_SGMII2 (0x20)
54 #define MASK_LANE_B 0x1
55 #define MASK_LANE_C 0x2
56 #define MASK_LANE_D 0x4
57 #define MASK_SGMII 0x8
59 #define KEEP_STATUS 0x0
60 #define NEED_RESET 0x1
62 #define SOFT_MUX_ON_I2C3_IFC 0x2
63 #define SOFT_MUX_ON_CAN3_USB2 0x8
64 #define SOFT_MUX_ON_QE_LCD 0x10
66 #define PIN_I2C3_IFC_MUX_I2C3 0x0
67 #define PIN_I2C3_IFC_MUX_IFC 0x1
68 #define PIN_CAN3_USB2_MUX_USB2 0x0
69 #define PIN_CAN3_USB2_MUX_CAN3 0x1
70 #define PIN_QE_LCD_MUX_LCD 0x0
71 #define PIN_QE_LCD_MUX_QE 0x1
74 u8 cpld_ver; /* cpld revision */
75 u8 cpld_ver_sub; /* cpld sub revision */
76 u8 pcba_ver; /* pcb revision number */
77 u8 system_rst; /* reset system by cpld */
78 u8 soft_mux_on; /* CPLD override physical switches Enable */
79 u8 cfg_rcw_src1; /* Reset config word 1 */
80 u8 cfg_rcw_src2; /* Reset config word 2 */
81 u8 vbank; /* Flash bank selection Control */
82 u8 gpio; /* GPIO for TWR-ELEV */
85 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
86 u8 qe_lcd_mux; /* QE and LCD Selection */
87 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
88 u8 global_rst; /* reset with init CPLD reg to default */
89 u8 rev1; /* Reserved */
90 u8 rev2; /* Reserved */
93 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
94 static void convert_serdes_mux(int type, int need_reset);
98 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
100 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
101 in_8(&cpld_data->cpld_ver) & VERSION_MASK,
102 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
103 in_8(&cpld_data->pcba_ver) & VERSION_MASK,
104 in_8(&cpld_data->vbank) & BANK_MASK);
107 printf("soft_mux_on =%x\n",
108 in_8(&cpld_data->soft_mux_on));
109 printf("cfg_rcw_src1 =%x\n",
110 in_8(&cpld_data->cfg_rcw_src1));
111 printf("cfg_rcw_src2 =%x\n",
112 in_8(&cpld_data->cfg_rcw_src2));
113 printf("vbank =%x\n",
114 in_8(&cpld_data->vbank));
116 in_8(&cpld_data->gpio));
117 printf("i2c3_ifc_mux =%x\n",
118 in_8(&cpld_data->i2c3_ifc_mux));
119 printf("mux_spi2 =%x\n",
120 in_8(&cpld_data->mux_spi2));
121 printf("can3_usb2_mux =%x\n",
122 in_8(&cpld_data->can3_usb2_mux));
123 printf("qe_lcd_mux =%x\n",
124 in_8(&cpld_data->qe_lcd_mux));
125 printf("serdes_mux =%x\n",
126 in_8(&cpld_data->serdes_mux));
133 puts("Board: LS1021ATWR\n");
134 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
141 unsigned int get_soc_major_rev(void)
143 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
144 unsigned int svr, major;
146 svr = in_be32(&gur->svr);
147 major = SVR_MAJ(svr);
152 void ddrmc_init(void)
154 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
157 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
159 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
160 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
162 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
163 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
164 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
165 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
166 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
167 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
169 #ifdef CONFIG_DEEP_SLEEP
170 if (is_warm_boot()) {
171 out_be32(&ddr->sdram_cfg_2,
172 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
173 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
174 out_be32(&ddr->init_ext_addr, (1 << 31));
176 /* DRAM VRef will not be trained */
177 out_be32(&ddr->ddr_cdr2,
178 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
182 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
183 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
186 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
187 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
189 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
191 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
193 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
194 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
196 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
198 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
199 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
201 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
204 #ifdef CONFIG_DEEP_SLEEP
205 if (is_warm_boot()) {
206 /* enter self-refresh */
207 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
208 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
209 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
211 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
214 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
216 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
218 #ifdef CONFIG_DEEP_SLEEP
219 if (is_warm_boot()) {
220 /* exit self-refresh */
221 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
222 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
223 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
230 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
234 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
236 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
243 #ifdef CONFIG_FSL_ESDHC
244 struct fsl_esdhc_cfg esdhc_cfg[1] = {
245 {CONFIG_SYS_FSL_ESDHC_ADDR},
248 int board_mmc_init(bd_t *bis)
250 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
252 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
256 #ifdef CONFIG_TSEC_ENET
257 int board_eth_init(bd_t *bis)
259 struct fsl_pq_mdio_info mdio_info;
260 struct tsec_info_struct tsec_info[4];
264 SET_STD_TSEC_INFO(tsec_info[num], 1);
265 if (is_serdes_configured(SGMII_TSEC1)) {
266 puts("eTSEC1 is in sgmii mode.\n");
267 tsec_info[num].flags |= TSEC_SGMII;
272 SET_STD_TSEC_INFO(tsec_info[num], 2);
273 if (is_serdes_configured(SGMII_TSEC2)) {
274 puts("eTSEC2 is in sgmii mode.\n");
275 tsec_info[num].flags |= TSEC_SGMII;
280 SET_STD_TSEC_INFO(tsec_info[num], 3);
284 printf("No TSECs initialized\n");
288 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
289 mdio_info.name = DEFAULT_MII_NAME;
290 fsl_pq_mdio_init(bis, &mdio_info);
292 tsec_eth_init(bis, tsec_info, num);
294 return pci_eth_init(bis);
298 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
299 int config_serdes_mux(void)
301 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
302 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
304 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
307 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
308 convert_serdes_mux(LANED_PCIEX2 |
309 LANEC_PCIEX1, KEEP_STATUS);
312 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
313 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
314 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
317 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
318 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
319 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
322 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
323 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
324 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
332 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
333 int config_board_mux(void)
335 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
339 if (hwconfig("i2c3")) {
341 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
342 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
345 if (hwconfig("ifc")) {
347 /* some signals can not enable simultaneous*/
348 if (conflict_flag > 1)
350 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
351 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
355 if (hwconfig("usb2")) {
357 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
358 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
361 if (hwconfig("can3")) {
363 /* some signals can not enable simultaneous*/
364 if (conflict_flag > 1)
366 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
367 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
371 if (hwconfig("lcd")) {
373 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
374 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
377 if (hwconfig("qe")) {
379 /* some signals can not enable simultaneous*/
380 if (conflict_flag > 1)
382 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
383 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
389 printf("WARNING: pin conflict! MUX setting may failed!\n");
394 int board_early_init_f(void)
396 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
397 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
400 #ifdef CONFIG_TSEC_ENET
401 /* clear BD & FR bits for BE BD's and frame data */
402 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
403 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
406 #ifdef CONFIG_FSL_IFC
407 init_early_memctl_regs();
410 #ifdef CONFIG_FSL_DCU_FB
411 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
414 #ifdef CONFIG_FSL_QSPI
415 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
418 /* Configure Little endian for SAI, ASRC and SPDIF */
419 out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
422 * Enable snoop requests and DVM message requests for
423 * Slave insterface S4 (A7 core cluster)
425 out_le32(&cci->slave[4].snoop_ctrl,
426 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
428 major = get_soc_major_rev();
429 if (major == SOC_MAJOR_VER_1_0) {
431 * Set CCI-400 Slave interface S1, S2 Shareable Override
432 * Register All transactions are treated as non-shareable
434 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
435 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
438 #if defined(CONFIG_DEEP_SLEEP)
440 fsl_dp_disable_console();
446 #ifdef CONFIG_SPL_BUILD
447 void board_init_f(ulong dummy)
450 memset(__bss_start, 0, __bss_end - __bss_start);
454 #if defined(CONFIG_DEEP_SLEEP)
456 fsl_dp_disable_console();
459 preloader_console_init();
463 /* Allow OCRAM access permission as R/W */
464 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
465 enable_layerscape_ns_access();
466 enable_layerscape_ns_access();
469 board_init_r(NULL, 0);
474 struct liodn_id_table sec_liodn_tbl[] = {
475 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
476 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
477 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
478 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
479 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
480 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
481 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
482 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
483 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
484 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
485 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
486 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
487 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
488 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
489 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
490 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
493 struct smmu_stream_id dev_stream_id[] = {
494 { 0x100, 0x01, "ETSEC MAC1" },
495 { 0x104, 0x02, "ETSEC MAC2" },
496 { 0x108, 0x03, "ETSEC MAC3" },
497 { 0x10c, 0x04, "PEX1" },
498 { 0x110, 0x05, "PEX2" },
499 { 0x114, 0x06, "qDMA" },
500 { 0x118, 0x07, "SATA" },
501 { 0x11c, 0x08, "USB3" },
502 { 0x120, 0x09, "QE" },
503 { 0x124, 0x0a, "eSDHC" },
504 { 0x128, 0x0b, "eMA" },
505 { 0x14c, 0x0c, "2D-ACE" },
506 { 0x150, 0x0d, "USB2" },
507 { 0x18c, 0x0e, "DEBUG" },
510 #ifdef CONFIG_DEEP_SLEEP
511 /* program the regulator (MC34VR500) to support deep sleep */
512 void ls1twr_program_regulator(void)
514 unsigned int i2c_bus;
517 #define LS1TWR_I2C_BUS_MC34VR500 1
518 #define MC34VR500_ADDR 0x8
519 #define MC34VR500_DEVICEID 0x4
520 #define MC34VR500_DEVICEID_MASK 0x0f
522 i2c_bus = i2c_get_bus_num();
523 i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
524 i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
525 MC34VR500_DEVICEID_MASK;
526 if (i2c_device_id != MC34VR500_DEVICEID) {
527 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
531 i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
532 i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
533 i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
534 i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
535 i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
537 i2c_set_bus_num(i2c_bus);
543 #ifndef CONFIG_SYS_FSL_NO_SERDES
545 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
550 ls1021x_config_caam_stream_id(sec_liodn_tbl,
551 ARRAY_SIZE(sec_liodn_tbl));
552 ls102xa_config_smmu_stream_id(dev_stream_id,
553 ARRAY_SIZE(dev_stream_id));
555 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
556 enable_layerscape_ns_access();
563 #ifdef CONFIG_DEEP_SLEEP
564 ls1twr_program_regulator();
569 #ifdef CONFIG_BOARD_LATE_INIT
570 int board_late_init(void)
572 #ifdef CONFIG_SCSI_AHCI_PLAT
580 #if defined(CONFIG_MISC_INIT_R)
581 int misc_init_r(void)
583 #ifdef CONFIG_FSL_DEVICE_DISABLE
584 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
586 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
590 #ifdef CONFIG_FSL_CAAM
596 #if defined(CONFIG_DEEP_SLEEP)
597 void board_sleep_prepare(void)
599 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
600 enable_layerscape_ns_access();
605 int ft_board_setup(void *blob, bd_t *bd)
607 ft_cpu_setup(blob, bd);
610 ft_pci_setup(blob, bd);
616 u8 flash_read8(void *addr)
618 return __raw_readb(addr + 1);
621 void flash_write16(u16 val, void *addr)
623 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
625 __raw_writew(shftval, addr);
628 u16 flash_read16(void *addr)
630 u16 val = __raw_readw(addr);
632 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
635 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
636 static void convert_flash_bank(char bank)
638 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
640 printf("Now switch to boot from flash bank %d.\n", bank);
641 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
642 cpld_data->vbank = bank;
644 printf("Reset board to enable configuration.\n");
645 cpld_data->system_rst = CONFIG_RESET;
648 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
652 return CMD_RET_USAGE;
653 if (strcmp(argv[1], "0") == 0)
654 convert_flash_bank(BOOT_FROM_UPPER_BANK);
655 else if (strcmp(argv[1], "1") == 0)
656 convert_flash_bank(BOOT_FROM_LOWER_BANK);
658 return CMD_RET_USAGE;
664 boot_bank, 2, 0, flash_bank_cmd,
665 "Flash bank Selection Control",
666 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
669 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
672 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
675 return CMD_RET_USAGE;
676 if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
677 cpld_data->system_rst = CONFIG_RESET;
678 else if (strcmp(argv[1], "init") == 0)
679 cpld_data->global_rst = INIT_RESET;
681 return CMD_RET_USAGE;
687 cpld_reset, 2, 0, cpld_reset_cmd,
690 " -reset with current CPLD configuration\n"
692 " -reset and initial CPLD configuration with default value"
696 static void convert_serdes_mux(int type, int need_reset)
699 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
701 current_serdes = cpld_data->serdes_mux;
705 current_serdes &= ~MASK_LANE_B;
708 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
711 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
714 current_serdes |= MASK_LANE_D;
717 current_serdes |= MASK_LANE_C;
719 case (LANED_PCIEX2 | LANEC_PCIEX1):
720 current_serdes |= MASK_LANE_C;
721 current_serdes &= ~MASK_LANE_D;
724 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
728 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
729 cpld_data->serdes_mux = current_serdes;
731 if (need_reset == 1) {
732 printf("Reset board to enable configuration\n");
733 cpld_data->system_rst = CONFIG_RESET;
737 void print_serdes_mux(void)
740 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
742 current_serdes = cpld_data->serdes_mux;
744 printf("Serdes Lane B: ");
745 if ((current_serdes & MASK_LANE_B) == 0)
748 printf("SGMII 1,\n");
750 printf("Serdes Lane C: ");
751 if ((current_serdes & MASK_LANE_C) == 0)
752 printf("SGMII 1,\n");
756 printf("Serdes Lane D: ");
757 if ((current_serdes & MASK_LANE_D) == 0)
760 printf("SGMII 2,\n");
762 printf("SGMII 1 is on lane ");
763 if ((current_serdes & MASK_SGMII) == 0)
769 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
773 return CMD_RET_USAGE;
774 if (strcmp(argv[1], "sata") == 0) {
775 printf("Set serdes lane B to SATA.\n");
776 convert_serdes_mux(LANEB_SATA, NEED_RESET);
777 } else if (strcmp(argv[1], "sgmii1b") == 0) {
778 printf("Set serdes lane B to SGMII 1.\n");
779 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
780 } else if (strcmp(argv[1], "sgmii1c") == 0) {
781 printf("Set serdes lane C to SGMII 1.\n");
782 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
783 } else if (strcmp(argv[1], "sgmii2") == 0) {
784 printf("Set serdes lane D to SGMII 2.\n");
785 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
786 } else if (strcmp(argv[1], "pciex1") == 0) {
787 printf("Set serdes lane C to PCIe X1.\n");
788 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
789 } else if (strcmp(argv[1], "pciex2") == 0) {
790 printf("Set serdes lane C & lane D to PCIe X2.\n");
791 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
792 } else if (strcmp(argv[1], "show") == 0) {
795 return CMD_RET_USAGE;
802 lane_bank, 2, 0, serdes_mux_cmd,
803 "Multiplexed function setting for SerDes Lanes",
805 " -change lane B to sata\n"
806 "lane_bank sgmii1b\n"
807 " -change lane B to SGMII1\n"
808 "lane_bank sgmii1c\n"
809 " -change lane C to SGMII1\n"
811 " -change lane D to SGMII2\n"
813 " -change lane C to PCIeX1\n"
815 " -change lane C & lane D to PCIeX2\n"
816 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"