2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
13 #include <fsl_dtsec.h>
16 #include <asm/arch/fsl_serdes.h>
18 #include "../common/qixis.h"
19 #include "../common/fman.h"
20 #include "ls1043aqds_qixis.h"
31 static int mdio_mux[NUM_FM_PORTS];
33 static const char * const mdio_names[] = {
34 "LS1043AQDS_MDIO_RGMII1",
35 "LS1043AQDS_MDIO_RGMII2",
36 "LS1043AQDS_MDIO_SLOT1",
37 "LS1043AQDS_MDIO_SLOT2",
38 "LS1043AQDS_MDIO_SLOT3",
39 "LS1043AQDS_MDIO_SLOT4",
43 /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
44 static u8 lane_to_slot[] = {1, 2, 3, 4};
46 static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
48 return mdio_names[muxval];
51 struct mii_dev *mii_dev_for_muxval(u8 muxval)
59 name = ls1043aqds_mdio_name_for_muxval(muxval);
62 printf("No bus for muxval %x\n", muxval);
66 bus = miiphy_get_dev_by_name(name);
69 printf("No bus by name %s\n", name);
76 struct ls1043aqds_mdio {
78 struct mii_dev *realbus;
81 static void ls1043aqds_mux_mdio(u8 muxval)
86 brdcfg4 = QIXIS_READ(brdcfg[4]);
87 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
88 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
89 QIXIS_WRITE(brdcfg[4], brdcfg4);
93 static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
96 struct ls1043aqds_mdio *priv = bus->priv;
98 ls1043aqds_mux_mdio(priv->muxval);
100 return priv->realbus->read(priv->realbus, addr, devad, regnum);
103 static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
104 int regnum, u16 value)
106 struct ls1043aqds_mdio *priv = bus->priv;
108 ls1043aqds_mux_mdio(priv->muxval);
110 return priv->realbus->write(priv->realbus, addr, devad,
114 static int ls1043aqds_mdio_reset(struct mii_dev *bus)
116 struct ls1043aqds_mdio *priv = bus->priv;
118 return priv->realbus->reset(priv->realbus);
121 static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
123 struct ls1043aqds_mdio *pmdio;
124 struct mii_dev *bus = mdio_alloc();
127 printf("Failed to allocate ls1043aqds MDIO bus\n");
131 pmdio = malloc(sizeof(*pmdio));
133 printf("Failed to allocate ls1043aqds private data\n");
138 bus->read = ls1043aqds_mdio_read;
139 bus->write = ls1043aqds_mdio_write;
140 bus->reset = ls1043aqds_mdio_reset;
141 strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
143 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
145 if (!pmdio->realbus) {
146 printf("No bus with name %s\n", realbusname);
152 pmdio->muxval = muxval;
154 return mdio_register(bus);
157 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
158 enum fm_port port, int offset)
160 struct fixed_link f_link;
162 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
163 if (port == FM1_DTSEC9) {
164 fdt_set_phy_handle(fdt, compat, addr,
165 "sgmii_riser_s1_p1");
166 } else if (port == FM1_DTSEC2) {
167 fdt_set_phy_handle(fdt, compat, addr,
168 "sgmii_riser_s2_p1");
169 } else if (port == FM1_DTSEC5) {
170 fdt_set_phy_handle(fdt, compat, addr,
171 "sgmii_riser_s3_p1");
172 } else if (port == FM1_DTSEC6) {
173 fdt_set_phy_handle(fdt, compat, addr,
174 "sgmii_riser_s4_p1");
176 } else if (fm_info_get_enet_if(port) ==
177 PHY_INTERFACE_MODE_SGMII_2500) {
178 /* 2.5G SGMII interface */
179 f_link.phy_id = cpu_to_fdt32(port);
180 f_link.duplex = cpu_to_fdt32(1);
181 f_link.link_speed = cpu_to_fdt32(1000);
183 f_link.asym_pause = 0;
184 /* no PHY for 2.5G SGMII */
185 fdt_delprop(fdt, offset, "phy-handle");
186 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
187 fdt_setprop_string(fdt, offset, "phy-connection-type",
189 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
190 switch (mdio_mux[port]) {
194 fdt_set_phy_handle(fdt, compat, addr,
198 fdt_set_phy_handle(fdt, compat, addr,
202 fdt_set_phy_handle(fdt, compat, addr,
206 fdt_set_phy_handle(fdt, compat, addr,
216 fdt_set_phy_handle(fdt, compat, addr,
220 fdt_set_phy_handle(fdt, compat, addr,
224 fdt_set_phy_handle(fdt, compat, addr,
228 fdt_set_phy_handle(fdt, compat, addr,
238 fdt_delprop(fdt, offset, "phy-connection-type");
239 fdt_setprop_string(fdt, offset, "phy-connection-type",
241 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
242 port == FM1_10GEC1) {
244 f_link.phy_id = cpu_to_fdt32(port);
245 f_link.duplex = cpu_to_fdt32(1);
246 f_link.link_speed = cpu_to_fdt32(10000);
248 f_link.asym_pause = 0;
250 fdt_delprop(fdt, offset, "phy-handle");
251 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
252 fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
256 void fdt_fixup_board_enet(void *fdt)
259 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
262 srds_s1 = in_be32(&gur->rcwsr[4]) &
263 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
264 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
266 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
267 switch (fm_info_get_enet_if(i)) {
268 case PHY_INTERFACE_MODE_SGMII:
269 case PHY_INTERFACE_MODE_QSGMII:
270 switch (mdio_mux[i]) {
272 fdt_status_okay_by_alias(fdt, "emi1_slot1");
275 fdt_status_okay_by_alias(fdt, "emi1_slot2");
278 fdt_status_okay_by_alias(fdt, "emi1_slot3");
281 fdt_status_okay_by_alias(fdt, "emi1_slot4");
287 case PHY_INTERFACE_MODE_XGMII:
295 int board_eth_init(bd_t *bis)
297 #ifdef CONFIG_FMAN_ENET
298 int i, idx, lane, slot, interface;
299 struct memac_mdio_info dtsec_mdio_info;
300 struct memac_mdio_info tgec_mdio_info;
301 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
304 srds_s1 = in_be32(&gur->rcwsr[4]) &
305 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
306 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
308 /* Initialize the mdio_mux array so we can recognize empty elements */
309 for (i = 0; i < NUM_FM_PORTS; i++)
310 mdio_mux[i] = EMI_NONE;
312 dtsec_mdio_info.regs =
313 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
315 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
317 /* Register the 1G MDIO bus */
318 fm_memac_mdio_init(bis, &dtsec_mdio_info);
320 tgec_mdio_info.regs =
321 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
322 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
324 /* Register the 10G MDIO bus */
325 fm_memac_mdio_init(bis, &tgec_mdio_info);
327 /* Register the muxing front-ends to the MDIO buses */
328 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
329 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
330 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
331 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
332 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
333 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
334 ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
336 /* Set the two on-board RGMII PHY address */
337 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
338 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
342 /* 2.5G SGMII on lane A, MAC 9 */
343 fm_info_set_phy_address(FM1_DTSEC9, 9);
347 /* QSGMII on lane A, MAC 1/2/5/6 */
348 fm_info_set_phy_address(FM1_DTSEC1,
349 QSGMII_CARD_PORT1_PHY_ADDR_S1);
350 fm_info_set_phy_address(FM1_DTSEC2,
351 QSGMII_CARD_PORT2_PHY_ADDR_S1);
352 fm_info_set_phy_address(FM1_DTSEC5,
353 QSGMII_CARD_PORT3_PHY_ADDR_S1);
354 fm_info_set_phy_address(FM1_DTSEC6,
355 QSGMII_CARD_PORT4_PHY_ADDR_S1);
358 /* SGMII on lane B, MAC 2*/
359 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
362 /* 2.5G SGMII on lane A, MAC 9 */
363 fm_info_set_phy_address(FM1_DTSEC9, 9);
364 /* SGMII on lane B, MAC 2*/
365 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
368 /* SGMII on lane C, MAC 5 */
369 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
372 /* SGMII on lane B, MAC 2 */
373 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
376 /* SGMII on lane A, MAC 9 */
377 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
380 /* QSGMII on lane B, MAC 1/2/5/6 */
381 fm_info_set_phy_address(FM1_DTSEC1,
382 QSGMII_CARD_PORT1_PHY_ADDR_S2);
383 fm_info_set_phy_address(FM1_DTSEC2,
384 QSGMII_CARD_PORT2_PHY_ADDR_S2);
385 fm_info_set_phy_address(FM1_DTSEC5,
386 QSGMII_CARD_PORT3_PHY_ADDR_S2);
387 fm_info_set_phy_address(FM1_DTSEC6,
388 QSGMII_CARD_PORT4_PHY_ADDR_S2);
391 /* 2.5G SGMII on lane A, MAC 9 */
392 fm_info_set_phy_address(FM1_DTSEC9, 9);
393 /* QSGMII on lane B, MAC 1/2/5/6 */
394 fm_info_set_phy_address(FM1_DTSEC1,
395 QSGMII_CARD_PORT1_PHY_ADDR_S2);
396 fm_info_set_phy_address(FM1_DTSEC2,
397 QSGMII_CARD_PORT2_PHY_ADDR_S2);
398 fm_info_set_phy_address(FM1_DTSEC5,
399 QSGMII_CARD_PORT3_PHY_ADDR_S2);
400 fm_info_set_phy_address(FM1_DTSEC6,
401 QSGMII_CARD_PORT4_PHY_ADDR_S2);
404 /* 2.5G SGMII on lane A, MAC 9 */
405 fm_info_set_phy_address(FM1_DTSEC9, 9);
406 /* 2.5G SGMII on lane B, MAC 2 */
407 fm_info_set_phy_address(FM1_DTSEC2, 2);
410 /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
411 fm_info_set_phy_address(FM1_DTSEC9,
412 SGMII_CARD_PORT1_PHY_ADDR);
413 fm_info_set_phy_address(FM1_DTSEC2,
414 SGMII_CARD_PORT1_PHY_ADDR);
415 fm_info_set_phy_address(FM1_DTSEC5,
416 SGMII_CARD_PORT1_PHY_ADDR);
417 fm_info_set_phy_address(FM1_DTSEC6,
418 SGMII_CARD_PORT1_PHY_ADDR);
421 printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
426 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
427 idx = i - FM1_DTSEC1;
428 interface = fm_info_get_enet_if(i);
430 case PHY_INTERFACE_MODE_SGMII:
431 case PHY_INTERFACE_MODE_SGMII_2500:
432 case PHY_INTERFACE_MODE_QSGMII:
433 if (interface == PHY_INTERFACE_MODE_SGMII) {
434 lane = serdes_get_first_lane(FSL_SRDS_1,
435 SGMII_FM1_DTSEC1 + idx);
436 } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
437 lane = serdes_get_first_lane(FSL_SRDS_1,
438 SGMII_2500_FM1_DTSEC1 + idx);
440 lane = serdes_get_first_lane(FSL_SRDS_1,
447 slot = lane_to_slot[lane];
448 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
450 if (QIXIS_READ(present2) & (1 << (slot - 1)))
455 mdio_mux[i] = EMI1_SLOT1;
456 fm_info_set_mdio(i, mii_dev_for_muxval(
460 mdio_mux[i] = EMI1_SLOT2;
461 fm_info_set_mdio(i, mii_dev_for_muxval(
465 mdio_mux[i] = EMI1_SLOT3;
466 fm_info_set_mdio(i, mii_dev_for_muxval(
470 mdio_mux[i] = EMI1_SLOT4;
471 fm_info_set_mdio(i, mii_dev_for_muxval(
478 case PHY_INTERFACE_MODE_RGMII:
480 mdio_mux[i] = EMI1_RGMII1;
481 else if (i == FM1_DTSEC4)
482 mdio_mux[i] = EMI1_RGMII2;
483 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
491 #endif /* CONFIG_FMAN_ENET */
493 return pci_eth_init(bis);