2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <fsl_dtsec.h>
14 #include <asm/arch/fsl_serdes.h>
16 #include "../common/qixis.h"
17 #include "../common/fman.h"
18 #include "ls1043aqds_qixis.h"
29 static int mdio_mux[NUM_FM_PORTS];
31 static const char * const mdio_names[] = {
32 "LS1043AQDS_MDIO_RGMII1",
33 "LS1043AQDS_MDIO_RGMII2",
34 "LS1043AQDS_MDIO_SLOT1",
35 "LS1043AQDS_MDIO_SLOT2",
36 "LS1043AQDS_MDIO_SLOT3",
37 "LS1043AQDS_MDIO_SLOT4",
41 /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
42 static u8 lane_to_slot[] = {1, 2, 3, 4};
44 static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
46 return mdio_names[muxval];
49 struct mii_dev *mii_dev_for_muxval(u8 muxval)
57 name = ls1043aqds_mdio_name_for_muxval(muxval);
60 printf("No bus for muxval %x\n", muxval);
64 bus = miiphy_get_dev_by_name(name);
67 printf("No bus by name %s\n", name);
74 struct ls1043aqds_mdio {
76 struct mii_dev *realbus;
79 static void ls1043aqds_mux_mdio(u8 muxval)
84 brdcfg4 = QIXIS_READ(brdcfg[4]);
85 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
86 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
87 QIXIS_WRITE(brdcfg[4], brdcfg4);
91 static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
94 struct ls1043aqds_mdio *priv = bus->priv;
96 ls1043aqds_mux_mdio(priv->muxval);
98 return priv->realbus->read(priv->realbus, addr, devad, regnum);
101 static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
102 int regnum, u16 value)
104 struct ls1043aqds_mdio *priv = bus->priv;
106 ls1043aqds_mux_mdio(priv->muxval);
108 return priv->realbus->write(priv->realbus, addr, devad,
112 static int ls1043aqds_mdio_reset(struct mii_dev *bus)
114 struct ls1043aqds_mdio *priv = bus->priv;
116 return priv->realbus->reset(priv->realbus);
119 static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
121 struct ls1043aqds_mdio *pmdio;
122 struct mii_dev *bus = mdio_alloc();
125 printf("Failed to allocate ls1043aqds MDIO bus\n");
129 pmdio = malloc(sizeof(*pmdio));
131 printf("Failed to allocate ls1043aqds private data\n");
136 bus->read = ls1043aqds_mdio_read;
137 bus->write = ls1043aqds_mdio_write;
138 bus->reset = ls1043aqds_mdio_reset;
139 strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
141 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
143 if (!pmdio->realbus) {
144 printf("No bus with name %s\n", realbusname);
150 pmdio->muxval = muxval;
152 return mdio_register(bus);
155 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
156 enum fm_port port, int offset)
158 struct fixed_link f_link;
160 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
161 if (port == FM1_DTSEC9) {
162 fdt_set_phy_handle(fdt, compat, addr,
163 "sgmii_riser_s1_p1");
164 } else if (port == FM1_DTSEC2) {
165 fdt_set_phy_handle(fdt, compat, addr,
166 "sgmii_riser_s2_p1");
167 } else if (port == FM1_DTSEC5) {
168 fdt_set_phy_handle(fdt, compat, addr,
169 "sgmii_riser_s3_p1");
170 } else if (port == FM1_DTSEC6) {
171 fdt_set_phy_handle(fdt, compat, addr,
172 "sgmii_riser_s4_p1");
174 } else if (fm_info_get_enet_if(port) ==
175 PHY_INTERFACE_MODE_SGMII_2500) {
176 /* 2.5G SGMII interface */
177 f_link.phy_id = port;
179 f_link.link_speed = 1000;
181 f_link.asym_pause = 0;
182 /* no PHY for 2.5G SGMII */
183 fdt_delprop(fdt, offset, "phy-handle");
184 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
185 fdt_setprop_string(fdt, offset, "phy-connection-type",
187 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
188 switch (mdio_mux[port]) {
192 fdt_set_phy_handle(fdt, compat, addr,
196 fdt_set_phy_handle(fdt, compat, addr,
200 fdt_set_phy_handle(fdt, compat, addr,
204 fdt_set_phy_handle(fdt, compat, addr,
214 fdt_set_phy_handle(fdt, compat, addr,
218 fdt_set_phy_handle(fdt, compat, addr,
222 fdt_set_phy_handle(fdt, compat, addr,
226 fdt_set_phy_handle(fdt, compat, addr,
236 fdt_delprop(fdt, offset, "phy-connection-type");
237 fdt_setprop_string(fdt, offset, "phy-connection-type",
239 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
240 port == FM1_10GEC1) {
242 f_link.phy_id = port;
244 f_link.link_speed = 10000;
246 f_link.asym_pause = 0;
248 fdt_delprop(fdt, offset, "phy-handle");
249 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
250 fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
254 void fdt_fixup_board_enet(void *fdt)
257 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
260 srds_s1 = in_be32(&gur->rcwsr[4]) &
261 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
262 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
264 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
265 switch (fm_info_get_enet_if(i)) {
266 case PHY_INTERFACE_MODE_SGMII:
267 case PHY_INTERFACE_MODE_QSGMII:
268 switch (mdio_mux[i]) {
270 fdt_status_okay_by_alias(fdt, "emi1_slot1");
273 fdt_status_okay_by_alias(fdt, "emi1_slot2");
276 fdt_status_okay_by_alias(fdt, "emi1_slot3");
279 fdt_status_okay_by_alias(fdt, "emi1_slot4");
285 case PHY_INTERFACE_MODE_XGMII:
293 int board_eth_init(bd_t *bis)
295 #ifdef CONFIG_FMAN_ENET
296 int i, idx, lane, slot, interface;
297 struct memac_mdio_info dtsec_mdio_info;
298 struct memac_mdio_info tgec_mdio_info;
299 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
302 srds_s1 = in_be32(&gur->rcwsr[4]) &
303 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
304 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
306 /* Initialize the mdio_mux array so we can recognize empty elements */
307 for (i = 0; i < NUM_FM_PORTS; i++)
308 mdio_mux[i] = EMI_NONE;
310 dtsec_mdio_info.regs =
311 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
313 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
315 /* Register the 1G MDIO bus */
316 fm_memac_mdio_init(bis, &dtsec_mdio_info);
318 tgec_mdio_info.regs =
319 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
320 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
322 /* Register the 10G MDIO bus */
323 fm_memac_mdio_init(bis, &tgec_mdio_info);
325 /* Register the muxing front-ends to the MDIO buses */
326 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
327 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
328 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
329 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
330 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
331 ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
332 ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
334 /* Set the two on-board RGMII PHY address */
335 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
336 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
340 /* 2.5G SGMII on lane A, MAC 9 */
341 fm_info_set_phy_address(FM1_DTSEC9, 9);
345 /* QSGMII on lane A, MAC 1/2/5/6 */
346 fm_info_set_phy_address(FM1_DTSEC1,
347 QSGMII_CARD_PORT1_PHY_ADDR_S1);
348 fm_info_set_phy_address(FM1_DTSEC2,
349 QSGMII_CARD_PORT2_PHY_ADDR_S1);
350 fm_info_set_phy_address(FM1_DTSEC5,
351 QSGMII_CARD_PORT3_PHY_ADDR_S1);
352 fm_info_set_phy_address(FM1_DTSEC6,
353 QSGMII_CARD_PORT4_PHY_ADDR_S1);
356 /* SGMII on lane B, MAC 2*/
357 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
360 /* 2.5G SGMII on lane A, MAC 9 */
361 fm_info_set_phy_address(FM1_DTSEC9, 9);
362 /* SGMII on lane B, MAC 2*/
363 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
366 /* SGMII on lane C, MAC 5 */
367 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
370 /* SGMII on lane B, MAC 2 */
371 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
374 /* SGMII on lane A, MAC 9 */
375 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
378 /* QSGMII on lane B, MAC 1/2/5/6 */
379 fm_info_set_phy_address(FM1_DTSEC1,
380 QSGMII_CARD_PORT1_PHY_ADDR_S2);
381 fm_info_set_phy_address(FM1_DTSEC2,
382 QSGMII_CARD_PORT2_PHY_ADDR_S2);
383 fm_info_set_phy_address(FM1_DTSEC5,
384 QSGMII_CARD_PORT3_PHY_ADDR_S2);
385 fm_info_set_phy_address(FM1_DTSEC6,
386 QSGMII_CARD_PORT4_PHY_ADDR_S2);
389 /* 2.5G SGMII on lane A, MAC 9 */
390 fm_info_set_phy_address(FM1_DTSEC9, 9);
391 /* QSGMII on lane B, MAC 1/2/5/6 */
392 fm_info_set_phy_address(FM1_DTSEC1,
393 QSGMII_CARD_PORT1_PHY_ADDR_S2);
394 fm_info_set_phy_address(FM1_DTSEC2,
395 QSGMII_CARD_PORT2_PHY_ADDR_S2);
396 fm_info_set_phy_address(FM1_DTSEC5,
397 QSGMII_CARD_PORT3_PHY_ADDR_S2);
398 fm_info_set_phy_address(FM1_DTSEC6,
399 QSGMII_CARD_PORT4_PHY_ADDR_S2);
402 /* 2.5G SGMII on lane A, MAC 9 */
403 fm_info_set_phy_address(FM1_DTSEC9, 9);
404 /* 2.5G SGMII on lane B, MAC 2 */
405 fm_info_set_phy_address(FM1_DTSEC2, 2);
408 /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
409 fm_info_set_phy_address(FM1_DTSEC9,
410 SGMII_CARD_PORT1_PHY_ADDR);
411 fm_info_set_phy_address(FM1_DTSEC2,
412 SGMII_CARD_PORT1_PHY_ADDR);
413 fm_info_set_phy_address(FM1_DTSEC5,
414 SGMII_CARD_PORT1_PHY_ADDR);
415 fm_info_set_phy_address(FM1_DTSEC6,
416 SGMII_CARD_PORT1_PHY_ADDR);
419 printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
424 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
425 idx = i - FM1_DTSEC1;
426 interface = fm_info_get_enet_if(i);
428 case PHY_INTERFACE_MODE_SGMII:
429 case PHY_INTERFACE_MODE_SGMII_2500:
430 case PHY_INTERFACE_MODE_QSGMII:
431 if (interface == PHY_INTERFACE_MODE_SGMII) {
432 lane = serdes_get_first_lane(FSL_SRDS_1,
433 SGMII_FM1_DTSEC1 + idx);
434 } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
435 lane = serdes_get_first_lane(FSL_SRDS_1,
436 SGMII_2500_FM1_DTSEC1 + idx);
438 lane = serdes_get_first_lane(FSL_SRDS_1,
445 slot = lane_to_slot[lane];
446 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
448 if (QIXIS_READ(present2) & (1 << (slot - 1)))
453 mdio_mux[i] = EMI1_SLOT1;
454 fm_info_set_mdio(i, mii_dev_for_muxval(
458 mdio_mux[i] = EMI1_SLOT2;
459 fm_info_set_mdio(i, mii_dev_for_muxval(
463 mdio_mux[i] = EMI1_SLOT3;
464 fm_info_set_mdio(i, mii_dev_for_muxval(
468 mdio_mux[i] = EMI1_SLOT4;
469 fm_info_set_mdio(i, mii_dev_for_muxval(
476 case PHY_INTERFACE_MODE_RGMII:
478 mdio_mux[i] = EMI1_RGMII1;
479 else if (i == FM1_DTSEC4)
480 mdio_mux[i] = EMI1_RGMII2;
481 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
489 #endif /* CONFIG_FMAN_ENET */
491 return pci_eth_init(bis);