2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
13 #include <fdt_support.h>
20 #include <fsl_esdhc.h>
27 #ifdef CONFIG_FSL_LS_PPA
28 #include <asm/arch/ppa.h>
31 DECLARE_GLOBAL_DATA_PTR;
35 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
36 #ifndef CONFIG_SD_BOOT
37 u8 cfg_rcw_src1, cfg_rcw_src2;
42 printf("Board: LS1043ARDB, boot from ");
47 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
48 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
49 cpld_rev_bit(&cfg_rcw_src1);
50 cfg_rcw_src = cfg_rcw_src1;
51 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
53 if (cfg_rcw_src == 0x25)
54 printf("vBank %d\n", CPLD_READ(vbank));
55 else if (cfg_rcw_src == 0x106)
58 printf("Invalid setting of SW4\n");
61 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
62 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
64 puts("SERDES Reference Clocks:\n");
65 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
66 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
73 gd->ram_size = initdram(0);
78 int board_early_init_f(void)
80 fsl_lsch2_early_init_f();
87 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
90 init_final_memctl_regs();
93 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
94 enable_layerscape_ns_access();
97 #ifdef CONFIG_FSL_LS_PPA
104 /* invert AQR105 IRQ pins polarity */
105 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
110 int config_board_mux(void)
112 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
115 if (hwconfig("qe-hdlc")) {
116 out_be32(&scfg->rcwpmuxcr0,
117 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
118 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
119 in_be32(&scfg->rcwpmuxcr0));
121 #ifdef CONFIG_HAS_FSL_XHCI_USB
122 out_be32(&scfg->rcwpmuxcr0, 0x3333);
123 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
124 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
125 SCFG_USBPWRFAULT_USB3_SHIFT) |
126 (SCFG_USBPWRFAULT_DEDICATED <<
127 SCFG_USBPWRFAULT_USB2_SHIFT) |
128 (SCFG_USBPWRFAULT_SHARED <<
129 SCFG_USBPWRFAULT_USB1_SHIFT);
130 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
136 #if defined(CONFIG_MISC_INIT_R)
137 int misc_init_r(void)
140 #ifdef CONFIG_SECURE_BOOT
141 /* In case of Secure Boot, the IBR configures the SMMU
142 * to allow only Secure transactions.
143 * SMMU must be reset in bypass mode.
144 * Set the ClientPD bit and Clear the USFCFG Bit
147 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
148 out_le32(SMMU_SCR0, val);
149 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
150 out_le32(SMMU_NSCR0, val);
152 #ifdef CONFIG_FSL_CAAM
159 void fdt_del_qe(void *blob)
163 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
165 fdt_del_node(blob, nodeoff);
169 int ft_board_setup(void *blob, bd_t *bd)
171 u64 base[CONFIG_NR_DRAM_BANKS];
172 u64 size[CONFIG_NR_DRAM_BANKS];
174 /* fixup DT for the two DDR banks */
175 base[0] = gd->bd->bi_dram[0].start;
176 size[0] = gd->bd->bi_dram[0].size;
177 base[1] = gd->bd->bi_dram[1].start;
178 size[1] = gd->bd->bi_dram[1].size;
180 fdt_fixup_memory_banks(blob, base, size, 2);
181 ft_cpu_setup(blob, bd);
183 #ifdef CONFIG_SYS_DPAA_FMAN
184 fdt_fixup_fman_ethernet(blob);
188 * qe-hdlc and usb multi-use the pins,
189 * when set hwconfig to qe-hdlc, delete usb node.
191 if (hwconfig("qe-hdlc"))
192 #ifdef CONFIG_HAS_FSL_XHCI_USB
193 fdt_del_node_and_alias(blob, "usb1");
196 * qe just support qe-uart and qe-hdlc,
197 * if qe-uart and qe-hdlc are not set in hwconfig,
200 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
206 u8 flash_read8(void *addr)
208 return __raw_readb(addr + 1);
211 void flash_write16(u16 val, void *addr)
213 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
215 __raw_writew(shftval, addr);
218 u16 flash_read16(void *addr)
220 u16 val = __raw_readw(addr);
222 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);