git.sur5r.net Git - u-boot/blob - board/freescale/ls1043ardb/ls1043ardb.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #include <asm/arch/soc.h>
  13 #include <fdt_support.h>
  14 #include <hwconfig.h>
  15 #include <ahci.h>
  16 #include <mmc.h>
  17 #include <scsi.h>
  18 #include <fm_eth.h>
  19 #include <fsl_esdhc.h>
  20 #include <fsl_ifc.h>
  21 #include <fsl_sec.h>
  22 #include "cpld.h"
  23 #ifdef CONFIG_U_QE
  24 #include <fsl_qe.h>
  25 #endif
  26 #ifdef CONFIG_FSL_LS_PPA
  27 #include <asm/arch/ppa.h>
  28 #endif
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 int checkboard(void)
  33 {
  34         static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
  35 #ifndef CONFIG_SD_BOOT
  36         u8 cfg_rcw_src1, cfg_rcw_src2;
  37         u16 cfg_rcw_src;
  38 #endif
  39         u8 sd1refclk_sel;
  40
  41         printf("Board: LS1043ARDB, boot from ");
  42
  43 #ifdef CONFIG_SD_BOOT
  44         puts("SD\n");
  45 #else
  46         cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
  47         cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
  48         cpld_rev_bit(&cfg_rcw_src1);
  49         cfg_rcw_src = cfg_rcw_src1;
  50         cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
  51
  52         if (cfg_rcw_src == 0x25)
  53                 printf("vBank %d\n", CPLD_READ(vbank));
  54         else if (cfg_rcw_src == 0x106)
  55                 puts("NAND\n");
  56         else
  57                 printf("Invalid setting of SW4\n");
  58 #endif
  59
  60         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
  61                CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
  62
  63         puts("SERDES Reference Clocks:\n");
  64         sd1refclk_sel = CPLD_READ(sd1refclk_sel);
  65         printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
  66
  67         return 0;
  68 }
  69
  70 int dram_init(void)
  71 {
  72         gd->ram_size = initdram(0);
  73
  74         return 0;
  75 }
  76
  77 int board_early_init_f(void)
  78 {
  79         fsl_lsch2_early_init_f();
  80
  81         return 0;
  82 }
  83
  84 int board_init(void)
  85 {
  86         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  87
  88 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  89         erratum_a010315();
  90 #endif
  91
  92 #ifdef CONFIG_FSL_IFC
  93         init_final_memctl_regs();
  94 #endif
  95
  96 #ifdef CONFIG_SECURE_BOOT
  97         /* In case of Secure Boot, the IBR configures the SMMU
  98          * to allow only Secure transactions.
  99          * SMMU must be reset in bypass mode.
 100          * Set the ClientPD bit and Clear the USFCFG Bit
 101          */
 102         u32 val;
 103         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 104         out_le32(SMMU_SCR0, val);
 105         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 106         out_le32(SMMU_NSCR0, val);
 107 #endif
 108
 109 #ifdef CONFIG_FSL_CAAM
 110         sec_init();
 111 #endif
 112
 113 #ifdef CONFIG_FSL_LS_PPA
 114         ppa_init();
 115 #endif
 116
 117 #ifdef CONFIG_U_QE
 118         u_qe_init();
 119 #endif
 120         /* invert AQR105 IRQ pins polarity */
 121         out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
 122
 123         return 0;
 124 }
 125
 126 int config_board_mux(void)
 127 {
 128         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 129         u32 usb_pwrfault;
 130
 131         if (hwconfig("qe-hdlc")) {
 132                 out_be32(&scfg->rcwpmuxcr0,
 133                          (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
 134                 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
 135                        in_be32(&scfg->rcwpmuxcr0));
 136         } else {
 137 #ifdef CONFIG_HAS_FSL_XHCI_USB
 138                 out_be32(&scfg->rcwpmuxcr0, 0x3333);
 139                 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 140                 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 141                                 SCFG_USBPWRFAULT_USB3_SHIFT) |
 142                                 (SCFG_USBPWRFAULT_DEDICATED <<
 143                                 SCFG_USBPWRFAULT_USB2_SHIFT) |
 144                                 (SCFG_USBPWRFAULT_SHARED <<
 145                                  SCFG_USBPWRFAULT_USB1_SHIFT);
 146                 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 147 #endif
 148         }
 149         return 0;
 150 }
 151
 152 #if defined(CONFIG_MISC_INIT_R)
 153 int misc_init_r(void)
 154 {
 155         config_board_mux();
 156         return 0;
 157 }
 158 #endif
 159
 160 void fdt_del_qe(void *blob)
 161 {
 162         int nodeoff = 0;
 163
 164         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 165                                 "fsl,qe")) >= 0) {
 166                 fdt_del_node(blob, nodeoff);
 167         }
 168 }
 169
 170 int ft_board_setup(void *blob, bd_t *bd)
 171 {
 172         u64 base[CONFIG_NR_DRAM_BANKS];
 173         u64 size[CONFIG_NR_DRAM_BANKS];
 174
 175         /* fixup DT for the two DDR banks */
 176         base[0] = gd->bd->bi_dram[0].start;
 177         size[0] = gd->bd->bi_dram[0].size;
 178         base[1] = gd->bd->bi_dram[1].start;
 179         size[1] = gd->bd->bi_dram[1].size;
 180
 181         fdt_fixup_memory_banks(blob, base, size, 2);
 182         ft_cpu_setup(blob, bd);
 183
 184 #ifdef CONFIG_SYS_DPAA_FMAN
 185         fdt_fixup_fman_ethernet(blob);
 186 #endif
 187
 188         /*
 189          * qe-hdlc and usb multi-use the pins,
 190          * when set hwconfig to qe-hdlc, delete usb node.
 191          */
 192         if (hwconfig("qe-hdlc"))
 193 #ifdef CONFIG_HAS_FSL_XHCI_USB
 194                 fdt_del_node_and_alias(blob, "usb1");
 195 #endif
 196         /*
 197          * qe just support qe-uart and qe-hdlc,
 198          * if qe-uart and qe-hdlc are not set in hwconfig,
 199          * delete qe node.
 200          */
 201         if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
 202                 fdt_del_qe(blob);
 203
 204         return 0;
 205 }
 206
 207 u8 flash_read8(void *addr)
 208 {
 209         return __raw_readb(addr + 1);
 210 }
 211
 212 void flash_write16(u16 val, void *addr)
 213 {
 214         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 215
 216         __raw_writew(shftval, addr);
 217 }
 218
 219 u16 flash_read16(void *addr)
 220 {
 221         u16 val = __raw_readw(addr);
 222
 223         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 224 }