2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/fdt.h>
14 #include <asm/arch/soc.h>
21 #include <fsl_esdhc.h>
25 #include "../common/vid.h"
26 #include "../common/qixis.h"
27 #include "ls1046aqds_qixis.h"
29 DECLARE_GLOBAL_DATA_PTR;
38 #ifndef CONFIG_SD_BOOT
42 puts("Board: LS1046AQDS, boot from ");
47 sw = QIXIS_READ(brdcfg[0]);
48 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
51 printf("vBank: %d\n", sw);
59 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
62 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
63 QIXIS_READ(id), QIXIS_READ(arch));
65 printf("FPGA: v%d (%s), build %d\n",
66 (int)QIXIS_READ(scver), qixis_read_tag(buf),
67 (int)qixis_read_minor());
72 bool if_board_diff_clk(void)
74 u8 diff_conf = QIXIS_READ(brdcfg[11]);
76 return diff_conf & 0x40;
79 unsigned long get_board_sys_clk(void)
81 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
83 switch (sysclk_conf & 0x0f) {
88 case QIXIS_SYSCLK_100:
90 case QIXIS_SYSCLK_125:
92 case QIXIS_SYSCLK_133:
94 case QIXIS_SYSCLK_150:
96 case QIXIS_SYSCLK_160:
98 case QIXIS_SYSCLK_166:
105 unsigned long get_board_ddr_clk(void)
107 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
109 if (if_board_diff_clk())
110 return get_board_sys_clk();
111 switch ((ddrclk_conf & 0x30) >> 4) {
112 case QIXIS_DDRCLK_100:
114 case QIXIS_DDRCLK_125:
116 case QIXIS_DDRCLK_133:
124 u32 get_lpuart_clk(void)
130 int select_i2c_ch_pca9547(u8 ch)
134 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
136 puts("PCA: failed to select proper channel\n");
146 * When resuming from deep sleep, the I2C channel may not be
147 * in the default channel. So, switch to the default channel
148 * before accessing DDR SPD.
150 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
151 gd->ram_size = initdram(0);
156 int i2c_multiplexer_select_vid_channel(u8 channel)
158 return select_i2c_ch_pca9547(channel);
161 int board_early_init_f(void)
163 #ifdef CONFIG_HAS_FSL_XHCI_USB
164 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
171 #ifdef CONFIG_SYS_I2C_EARLY_INIT
174 fsl_lsch2_early_init_f();
176 #ifdef CONFIG_HAS_FSL_XHCI_USB
177 out_be32(&scfg->rcwpmuxcr0, 0x3333);
178 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
179 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
180 SCFG_USBPWRFAULT_USB3_SHIFT) |
181 (SCFG_USBPWRFAULT_DEDICATED <<
182 SCFG_USBPWRFAULT_USB2_SHIFT) |
183 (SCFG_USBPWRFAULT_SHARED <<
184 SCFG_USBPWRFAULT_USB1_SHIFT);
185 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
189 /* We use lpuart0 as system console */
190 uart = QIXIS_READ(brdcfg[14]);
191 uart &= ~CFG_UART_MUX_MASK;
192 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
193 QIXIS_WRITE(brdcfg[14], uart);
199 #ifdef CONFIG_FSL_DEEP_SLEEP
200 /* determine if it is a warm boot */
201 bool is_warm_boot(void)
203 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
204 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
206 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
213 int config_board_mux(int ctrl_type)
217 reg14 = QIXIS_READ(brdcfg[14]);
221 reg14 = (reg14 & (~0x6)) | 0x2;
224 puts("Unsupported mux interface type\n");
228 QIXIS_WRITE(brdcfg[14], reg14);
233 int config_serdes_mux(void)
238 #ifdef CONFIG_MISC_INIT_R
239 int misc_init_r(void)
241 if (hwconfig("gpio"))
242 config_board_mux(MUX_TYPE_GPIO);
250 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
252 #ifdef CONFIG_SYS_FSL_SERDES
256 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
257 enable_layerscape_ns_access();
261 printf("Warning: Adjusting core voltage failed.\n");
266 #ifdef CONFIG_OF_BOARD_SETUP
267 int ft_board_setup(void *blob, bd_t *bd)
269 u64 base[CONFIG_NR_DRAM_BANKS];
270 u64 size[CONFIG_NR_DRAM_BANKS];
273 /* fixup DT for the two DDR banks */
274 base[0] = gd->bd->bi_dram[0].start;
275 size[0] = gd->bd->bi_dram[0].size;
276 base[1] = gd->bd->bi_dram[1].start;
277 size[1] = gd->bd->bi_dram[1].size;
279 fdt_fixup_memory_banks(blob, base, size, 2);
280 ft_cpu_setup(blob, bd);
282 #ifdef CONFIG_SYS_DPAA_FMAN
283 fdt_fixup_fman_ethernet(blob);
284 fdt_fixup_board_enet(blob);
287 reg = QIXIS_READ(brdcfg[0]);
288 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
290 /* Disable IFC if QSPI is enabled */
292 do_fixup_by_compat(blob, "fsl,ifc",
293 "status", "disabled", 8 + 1, 1);
299 u8 flash_read8(void *addr)
301 return __raw_readb(addr + 1);
304 void flash_write16(u16 val, void *addr)
306 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
308 __raw_writew(shftval, addr);
311 u16 flash_read16(void *addr)
313 u16 val = __raw_readw(addr);
315 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);