2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/fdt.h>
14 #include <asm/arch/mmu.h>
15 #include <asm/arch/soc.h>
22 #include <fsl_esdhc.h>
26 #include "../common/vid.h"
27 #include "../common/qixis.h"
28 #include "ls1046aqds_qixis.h"
30 DECLARE_GLOBAL_DATA_PTR;
39 #ifndef CONFIG_SD_BOOT
43 puts("Board: LS1046AQDS, boot from ");
48 sw = QIXIS_READ(brdcfg[0]);
49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
52 printf("vBank: %d\n", sw);
60 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
63 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
64 QIXIS_READ(id), QIXIS_READ(arch));
66 printf("FPGA: v%d (%s), build %d\n",
67 (int)QIXIS_READ(scver), qixis_read_tag(buf),
68 (int)qixis_read_minor());
73 bool if_board_diff_clk(void)
75 u8 diff_conf = QIXIS_READ(brdcfg[11]);
77 return diff_conf & 0x40;
80 unsigned long get_board_sys_clk(void)
82 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
84 switch (sysclk_conf & 0x0f) {
89 case QIXIS_SYSCLK_100:
91 case QIXIS_SYSCLK_125:
93 case QIXIS_SYSCLK_133:
95 case QIXIS_SYSCLK_150:
97 case QIXIS_SYSCLK_160:
99 case QIXIS_SYSCLK_166:
106 unsigned long get_board_ddr_clk(void)
108 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
110 if (if_board_diff_clk())
111 return get_board_sys_clk();
112 switch ((ddrclk_conf & 0x30) >> 4) {
113 case QIXIS_DDRCLK_100:
115 case QIXIS_DDRCLK_125:
117 case QIXIS_DDRCLK_133:
125 u32 get_lpuart_clk(void)
131 int select_i2c_ch_pca9547(u8 ch)
135 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
137 puts("PCA: failed to select proper channel\n");
147 * When resuming from deep sleep, the I2C channel may not be
148 * in the default channel. So, switch to the default channel
149 * before accessing DDR SPD.
151 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
153 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
154 /* This will break-before-make MMU for DDR */
155 update_early_mmu_table();
161 int i2c_multiplexer_select_vid_channel(u8 channel)
163 return select_i2c_ch_pca9547(channel);
166 int board_early_init_f(void)
168 #ifdef CONFIG_HAS_FSL_XHCI_USB
169 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
176 #ifdef CONFIG_SYS_I2C_EARLY_INIT
179 fsl_lsch2_early_init_f();
181 #ifdef CONFIG_HAS_FSL_XHCI_USB
182 out_be32(&scfg->rcwpmuxcr0, 0x3333);
183 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
184 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
185 SCFG_USBPWRFAULT_USB3_SHIFT) |
186 (SCFG_USBPWRFAULT_DEDICATED <<
187 SCFG_USBPWRFAULT_USB2_SHIFT) |
188 (SCFG_USBPWRFAULT_SHARED <<
189 SCFG_USBPWRFAULT_USB1_SHIFT);
190 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
194 /* We use lpuart0 as system console */
195 uart = QIXIS_READ(brdcfg[14]);
196 uart &= ~CFG_UART_MUX_MASK;
197 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
198 QIXIS_WRITE(brdcfg[14], uart);
204 #ifdef CONFIG_FSL_DEEP_SLEEP
205 /* determine if it is a warm boot */
206 bool is_warm_boot(void)
208 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
209 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
211 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
218 int config_board_mux(int ctrl_type)
222 reg14 = QIXIS_READ(brdcfg[14]);
226 reg14 = (reg14 & (~0x6)) | 0x2;
229 puts("Unsupported mux interface type\n");
233 QIXIS_WRITE(brdcfg[14], reg14);
238 int config_serdes_mux(void)
243 #ifdef CONFIG_MISC_INIT_R
244 int misc_init_r(void)
246 if (hwconfig("gpio"))
247 config_board_mux(MUX_TYPE_GPIO);
255 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
257 #ifdef CONFIG_SYS_FSL_SERDES
261 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
262 enable_layerscape_ns_access();
266 printf("Warning: Adjusting core voltage failed.\n");
271 #ifdef CONFIG_OF_BOARD_SETUP
272 int ft_board_setup(void *blob, bd_t *bd)
274 u64 base[CONFIG_NR_DRAM_BANKS];
275 u64 size[CONFIG_NR_DRAM_BANKS];
278 /* fixup DT for the two DDR banks */
279 base[0] = gd->bd->bi_dram[0].start;
280 size[0] = gd->bd->bi_dram[0].size;
281 base[1] = gd->bd->bi_dram[1].start;
282 size[1] = gd->bd->bi_dram[1].size;
284 fdt_fixup_memory_banks(blob, base, size, 2);
285 ft_cpu_setup(blob, bd);
287 #ifdef CONFIG_SYS_DPAA_FMAN
288 fdt_fixup_fman_ethernet(blob);
289 fdt_fixup_board_enet(blob);
292 reg = QIXIS_READ(brdcfg[0]);
293 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
295 /* Disable IFC if QSPI is enabled */
297 do_fixup_by_compat(blob, "fsl,ifc",
298 "status", "disabled", 8 + 1, 1);
304 u8 flash_read8(void *addr)
306 return __raw_readb(addr + 1);
309 void flash_write16(u16 val, void *addr)
311 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
313 __raw_writew(shftval, addr);
316 u16 flash_read16(void *addr)
318 u16 val = __raw_readw(addr);
320 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);