1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
7 #include <fsl_ddr_sdram.h>
8 #include <fsl_ddr_dimm_params.h>
10 #ifdef CONFIG_FSL_DEEP_SLEEP
11 #include <fsl_sleep.h>
13 #include <asm/arch/clock.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 void fsl_ddr_board_options(memctl_options_t *popts,
19 unsigned int ctrl_num)
21 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
25 printf("Not supported controller number %d\n", ctrl_num);
31 if (popts->registered_dimm_en)
36 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
37 * freqency and n_banks specified in board_specific_parameters table.
39 ddr_freq = get_ddr_freq(0) / 1000000;
40 while (pbsp->datarate_mhz_high) {
41 if (pbsp->n_ranks == pdimm->n_ranks) {
42 if (ddr_freq <= pbsp->datarate_mhz_high) {
43 popts->clk_adjust = pbsp->clk_adjust;
44 popts->wrlvl_start = pbsp->wrlvl_start;
45 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
46 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
55 printf("Error: board specific timing not found for %lu MT/s\n",
57 printf("Trying to use the highest speed (%u) parameters\n",
58 pbsp_highest->datarate_mhz_high);
59 popts->clk_adjust = pbsp_highest->clk_adjust;
60 popts->wrlvl_start = pbsp_highest->wrlvl_start;
61 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
62 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
64 panic("DIMM is not supported by this board");
67 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
68 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
70 popts->data_bus_width = 0; /* 64-bit data bus */
71 popts->bstopre = 0; /* enable auto precharge */
74 * Factors to consider for half-strength driver enable:
75 * - number of DIMMs installed
77 popts->half_strength_driver_enable = 0;
79 * Write leveling override
81 popts->wrlvl_override = 1;
82 popts->wrlvl_sample = 0xf;
85 * Rtt and Rtt_WR override
87 popts->rtt_override = 0;
89 /* Enable ZQ calibration */
92 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
93 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
94 DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
96 /* optimize cpo for erratum A-009942 */
97 popts->cpo_sample = 0x61;
100 int fsl_initdram(void)
102 phys_size_t dram_size;
104 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
105 gd->ram_size = fsl_ddr_sdram_size();
109 puts("Initializing DDR....using SPD\n");
111 dram_size = fsl_ddr_sdram();
114 erratum_a008850_post();
116 gd->ram_size = dram_size;