git.sur5r.net Git - u-boot/blob - board/freescale/ls1088a/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <fsl_ddr_sdram.h>
   8 #include <fsl_ddr_dimm_params.h>
   9 #include <asm/arch/soc.h>
  10 #include <asm/arch/clock.h>
  11 #include "ddr.h"
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  16 static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts)
  17 {
  18         int vdd;
  19
  20         vdd = get_core_volt_from_fuse();
  21         /* Nothing to do for silicons doesn't support VID */
  22         if (vdd < 0)
  23                 return;
  24
  25         if (vdd == 900) {
  26                 popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN;
  27                 debug("VID: configure DDR to support 900 mV\n");
  28         }
  29 }
  30 #endif
  31
  32 void fsl_ddr_board_options(memctl_options_t *popts,
  33                            dimm_params_t *pdimm,
  34                            unsigned int ctrl_num)
  35 {
  36         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  37         ulong ddr_freq;
  38
  39         if (ctrl_num > 1) {
  40                 printf("Not supported controller number %d\n", ctrl_num);
  41                 return;
  42         }
  43         if (!pdimm->n_ranks)
  44                 return;
  45
  46         /*
  47          * we use identical timing for all slots. If needed, change the code
  48          * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  49          */
  50         pbsp = udimms[0];
  51
  52         /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  53          * freqency and n_banks specified in board_specific_parameters table.
  54          */
  55         ddr_freq = get_ddr_freq(0) / 1000000;
  56         while (pbsp->datarate_mhz_high) {
  57                 if (pbsp->n_ranks == pdimm->n_ranks) {
  58                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  59                                 popts->clk_adjust = pbsp->clk_adjust;
  60                                 popts->wrlvl_start = pbsp->wrlvl_start;
  61                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  62                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  63                                 goto found;
  64                         }
  65                         pbsp_highest = pbsp;
  66                 }
  67                 pbsp++;
  68         }
  69
  70         if (pbsp_highest) {
  71                 printf("Error: board specific timing not found for %lu MT/s\n",
  72                        ddr_freq);
  73                 printf("Trying to use the highest speed (%u) parameters\n",
  74                        pbsp_highest->datarate_mhz_high);
  75                 popts->clk_adjust = pbsp_highest->clk_adjust;
  76                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  77                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  78                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  79         } else {
  80                 panic("DIMM is not supported by this board");
  81         }
  82 found:
  83         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  84                 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  85                 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  86                 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  87                 pbsp->wrlvl_ctl_3);
  88
  89
  90
  91         popts->half_strength_driver_enable = 0;
  92         /*
  93          * Write leveling override
  94          */
  95         popts->wrlvl_override = 1;
  96         popts->wrlvl_sample = 0xf;
  97
  98
  99         /* Enable ZQ calibration */
 100         popts->zq_en = 1;
 101
 102         /* Enable DDR hashing */
 103         popts->addr_hash = 1;
 104
 105         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
 106 #if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 107         fsl_ddr_setup_0v9_volt(popts);
 108 #endif
 109
 110         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
 111                           DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
 112 }
 113
 114
 115 int fsl_initdram(void)
 116 {
 117         puts("Initializing DDR....using SPD\n");
 118
 119 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 120         gd->ram_size = fsl_ddr_sdram_size();
 121 #else
 122         gd->ram_size = fsl_ddr_sdram();
 123 #endif
 124         return 0;
 125 }