git.sur5r.net Git - u-boot/blob - board/freescale/ls1088a/ddr.c

   1 /*
   2  * Copyright 2017 NXP
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <fsl_ddr_sdram.h>
   9 #include <fsl_ddr_dimm_params.h>
  10 #include <asm/arch/soc.h>
  11 #include <asm/arch/clock.h>
  12 #include "ddr.h"
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 void fsl_ddr_board_options(memctl_options_t *popts,
  17                            dimm_params_t *pdimm,
  18                            unsigned int ctrl_num)
  19 {
  20         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  21         ulong ddr_freq;
  22
  23         if (ctrl_num > 1) {
  24                 printf("Not supported controller number %d\n", ctrl_num);
  25                 return;
  26         }
  27         if (!pdimm->n_ranks)
  28                 return;
  29
  30         /*
  31          * we use identical timing for all slots. If needed, change the code
  32          * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  33          */
  34         pbsp = udimms[0];
  35
  36         /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  37          * freqency and n_banks specified in board_specific_parameters table.
  38          */
  39         ddr_freq = get_ddr_freq(0) / 1000000;
  40         while (pbsp->datarate_mhz_high) {
  41                 if (pbsp->n_ranks == pdimm->n_ranks) {
  42                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  43                                 popts->clk_adjust = pbsp->clk_adjust;
  44                                 popts->wrlvl_start = pbsp->wrlvl_start;
  45                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  46                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  47                                 goto found;
  48                         }
  49                         pbsp_highest = pbsp;
  50                 }
  51                 pbsp++;
  52         }
  53
  54         if (pbsp_highest) {
  55                 printf("Error: board specific timing not found for %lu MT/s\n",
  56                        ddr_freq);
  57                 printf("Trying to use the highest speed (%u) parameters\n",
  58                        pbsp_highest->datarate_mhz_high);
  59                 popts->clk_adjust = pbsp_highest->clk_adjust;
  60                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  61                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  62                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  63         } else {
  64                 panic("DIMM is not supported by this board");
  65         }
  66 found:
  67         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  68                 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  69                 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  70                 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  71                 pbsp->wrlvl_ctl_3);
  72
  73
  74
  75         popts->half_strength_driver_enable = 0;
  76         /*
  77          * Write leveling override
  78          */
  79         popts->wrlvl_override = 1;
  80         popts->wrlvl_sample = 0xf;
  81
  82
  83         /* Enable ZQ calibration */
  84         popts->zq_en = 1;
  85
  86         /* Enable DDR hashing */
  87         popts->addr_hash = 1;
  88
  89         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
  90         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
  91                           DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
  92 }
  93
  94
  95 int fsl_initdram(void)
  96 {
  97         puts("Initializing DDR....using SPD\n");
  98
  99 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 100         gd->ram_size = fsl_ddr_sdram_size();
 101 #else
 102         gd->ram_size = fsl_ddr_sdram();
 103 #endif
 104         return 0;
 105 }