4 * SPDX-License-Identifier: GPL-2.0+
15 #include <fdt_support.h>
16 #include <linux/libfdt.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h>
19 #include <asm/arch-fsl-layerscape/soc.h>
20 #include <asm/arch/ppa.h>
22 #include <asm/arch/fsl_serdes.h>
23 #include <asm/arch/soc.h>
25 #include "../common/qixis.h"
26 #include "ls1088a_qixis.h"
27 #include "../common/vid.h"
28 #include <fsl_immap.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 int board_early_init_f(void)
34 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
37 fsl_lsch3_early_init_f();
41 #ifdef CONFIG_FSL_QIXIS
42 unsigned long long get_qixis_addr(void)
44 unsigned long long addr;
46 if (gd->flags & GD_FLG_RELOC)
47 addr = QIXIS_BASE_PHYS;
49 addr = QIXIS_BASE_PHYS_EARLY;
52 * IFC address under 256MB is mapped to 0x30000000, any address above
53 * is mapped to 0x5_10000000 up to 4GB.
55 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
61 #if defined(CONFIG_VID)
62 int init_func_vid(void)
64 if (adjust_vdd(0) < 0)
65 printf("core voltage not adjusted\n");
71 #if !defined(CONFIG_SPL_BUILD)
76 static const char *const freq[] = {"100", "125", "156.25",
80 #ifdef CONFIG_TARGET_LS1088AQDS
81 printf("Board: LS1088A-QDS, ");
83 printf("Board: LS1088A-RDB, ");
86 sw = QIXIS_READ(arch);
87 printf("Board Arch: V%d, ", sw >> 4);
89 #ifdef CONFIG_TARGET_LS1088AQDS
90 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
92 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
95 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
97 sw = QIXIS_READ(brdcfg[0]);
98 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
100 #ifdef CONFIG_SD_BOOT
104 #ifdef CONFIG_TARGET_LS1088AQDS
113 printf("vBank: %d\n", sw);
126 sw = QIXIS_READ(brdcfg[0]);
127 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
128 if (sw == 0 || sw == 4)
137 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
141 #ifdef CONFIG_TARGET_LS1088AQDS
142 printf("FPGA: v%d (%s), build %d",
143 (int)QIXIS_READ(scver), qixis_read_tag(buf),
144 (int)qixis_read_minor());
145 /* the timestamp string contains "\n" at the end */
146 printf(" on %s", qixis_read_time(buf));
148 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
152 * Display the actual SERDES reference clocks as configured by the
153 * dip switches on the board. Note that the SWx registers could
154 * technically be set to force the reference clocks to match the
155 * values that the SERDES expects (or vice versa). For now, however,
156 * we just display both values and hope the user notices when they
159 puts("SERDES1 Reference : ");
160 sw = QIXIS_READ(brdcfg[2]);
161 clock = (sw >> 6) & 3;
162 printf("Clock1 = %sMHz ", freq[clock]);
163 clock = (sw >> 4) & 3;
164 printf("Clock2 = %sMHz", freq[clock]);
166 puts("\nSERDES2 Reference : ");
167 clock = (sw >> 2) & 3;
168 printf("Clock1 = %sMHz ", freq[clock]);
169 clock = (sw >> 0) & 3;
170 printf("Clock2 = %sMHz\n", freq[clock]);
176 bool if_board_diff_clk(void)
178 #ifdef CONFIG_TARGET_LS1088AQDS
179 u8 diff_conf = QIXIS_READ(brdcfg[11]);
180 return diff_conf & 0x40;
182 u8 diff_conf = QIXIS_READ(dutcfg[11]);
183 return diff_conf & 0x80;
187 unsigned long get_board_sys_clk(void)
189 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
191 switch (sysclk_conf & 0x0f) {
192 case QIXIS_SYSCLK_83:
194 case QIXIS_SYSCLK_100:
196 case QIXIS_SYSCLK_125:
198 case QIXIS_SYSCLK_133:
200 case QIXIS_SYSCLK_150:
202 case QIXIS_SYSCLK_160:
204 case QIXIS_SYSCLK_166:
211 unsigned long get_board_ddr_clk(void)
213 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
215 if (if_board_diff_clk())
216 return get_board_sys_clk();
217 switch ((ddrclk_conf & 0x30) >> 4) {
218 case QIXIS_DDRCLK_100:
220 case QIXIS_DDRCLK_125:
222 case QIXIS_DDRCLK_133:
229 int select_i2c_ch_pca9547(u8 ch)
233 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
235 puts("PCA: failed to select proper channel\n");
242 #if !defined(CONFIG_SPL_BUILD)
243 void board_retimer_init(void)
247 /* Retimer is connected to I2C1_CH5 */
248 select_i2c_ch_pca9547(I2C_MUX_CH5);
250 /* Access to Control/Shared register */
252 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
254 /* Read device revision and ID */
255 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
256 debug("Retimer version id = 0x%x\n", reg);
258 /* Enable Broadcast. All writes target all channel register sets */
260 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
262 /* Reset Channel Registers */
263 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
265 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
267 /* Set data rate as 10.3125 Gbps */
269 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
271 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
273 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
275 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
277 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
279 /* Select VCO Divider to full rate (000) */
280 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
283 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
285 #ifdef CONFIG_TARGET_LS1088AQDS
286 /* Retimer is connected to I2C1_CH5 */
287 select_i2c_ch_pca9547(I2C_MUX_CH5);
289 /* Access to Control/Shared register */
291 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
293 /* Read device revision and ID */
294 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
295 debug("Retimer version id = 0x%x\n", reg);
297 /* Enable Broadcast. All writes target all channel register sets */
299 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
301 /* Reset Channel Registers */
302 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
304 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
306 /* Set data rate as 10.3125 Gbps */
308 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
310 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
312 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
314 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
316 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
318 /* Select VCO Divider to full rate (000) */
319 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
322 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
324 /*return the default channel*/
325 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
328 #ifdef CONFIG_MISC_INIT_R
329 int misc_init_r(void)
331 #ifdef CONFIG_TARGET_LS1088ARDB
334 if (hwconfig("esdhc-force-sd")) {
335 brdcfg5 = QIXIS_READ(brdcfg[5]);
336 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
337 brdcfg5 |= BRDCFG5_FORCE_SD;
338 QIXIS_WRITE(brdcfg[5], brdcfg5);
346 int i2c_multiplexer_select_vid_channel(u8 channel)
348 return select_i2c_ch_pca9547(channel);
351 #ifdef CONFIG_TARGET_LS1088AQDS
352 /* read the current value(SVDD) of the LTM Regulator Voltage */
353 int get_serdes_volt(void)
356 u8 chan = PWM_CHANNEL0;
358 /* Select the PAGE 0 using PMBus commands PAGE for VDD */
359 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
360 PMBUS_CMD_PAGE, 1, &chan, 1);
362 printf("VID: failed to select VDD Page 0\n");
366 /* Read the output voltage using PMBus command READ_VOUT */
367 ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
368 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
370 printf("VID: failed to read the volatge\n");
377 int set_serdes_volt(int svdd)
380 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
381 svdd & 0xFF, (svdd & 0xFF00) >> 8};
383 /* Write the desired voltage code to the SVDD regulator */
384 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
385 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
387 printf("VID: I2C failed to write to the volatge regulator\n");
391 /* Wait for the volatge to get to the desired value */
393 vdd_last = get_serdes_volt();
395 printf("VID: Couldn't read sensor abort VID adjust\n");
398 } while (vdd_last != svdd);
403 int get_serdes_volt(void)
408 int set_serdes_volt(int svdd)
413 printf("SVDD changing of RDB\n");
415 /* Read the BRDCFG54 via CLPD */
416 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
417 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
419 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
423 brdcfg4 = brdcfg4 | 0x08;
425 /* Write to the BRDCFG4 */
426 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
427 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
429 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
433 /* Wait for the volatge to get to the desired value */
440 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
441 int board_adjust_vdd(int vdd)
445 debug("%s: vdd = %d\n", __func__, vdd);
447 /* Special settings to be performed when voltage is 900mV */
449 ret = setup_serdes_volt(vdd);
459 #if !defined(CONFIG_SPL_BUILD)
462 init_final_memctl_regs();
463 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
464 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
467 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
468 board_retimer_init();
470 #ifdef CONFIG_ENV_IS_NOWHERE
471 gd->env_addr = (ulong)&default_environment[0];
474 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
475 /* invert AQR105 IRQ pins polarity */
476 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
479 #ifdef CONFIG_FSL_CAAM
482 #ifdef CONFIG_FSL_LS_PPA
488 void detail_board_ddr_info(void)
491 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
495 #if defined(CONFIG_ARCH_MISC_INIT)
496 int arch_misc_init(void)
502 #ifdef CONFIG_FSL_MC_ENET
503 void fdt_fixup_board_enet(void *fdt)
507 offset = fdt_path_offset(fdt, "/fsl-mc");
510 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
513 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
518 if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
519 fdt_status_okay(fdt, offset);
521 fdt_status_fail(fdt, offset);
525 #ifdef CONFIG_OF_BOARD_SETUP
526 void fsl_fdt_fixup_flash(void *fdt)
531 * IFC-NOR and QSPI are muxed on SoC.
532 * So disable IFC node in dts if QSPI is enabled or
533 * disable QSPI node in dts in case QSPI is not enabled.
536 #ifdef CONFIG_FSL_QSPI
537 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
540 offset = fdt_path_offset(fdt, "/ifc/nor");
542 offset = fdt_path_offset(fdt, "/soc/quadspi");
545 offset = fdt_path_offset(fdt, "/quadspi");
550 fdt_status_disabled(fdt, offset);
553 int ft_board_setup(void *blob, bd_t *bd)
556 u64 base[CONFIG_NR_DRAM_BANKS];
557 u64 size[CONFIG_NR_DRAM_BANKS];
559 ft_cpu_setup(blob, bd);
561 /* fixup DT for the two GPP DDR banks */
562 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
563 base[i] = gd->bd->bi_dram[i].start;
564 size[i] = gd->bd->bi_dram[i].size;
567 #ifdef CONFIG_RESV_RAM
568 /* reduce size if reserved memory is within this bank */
569 if (gd->arch.resv_ram >= base[0] &&
570 gd->arch.resv_ram < base[0] + size[0])
571 size[0] = gd->arch.resv_ram - base[0];
572 else if (gd->arch.resv_ram >= base[1] &&
573 gd->arch.resv_ram < base[1] + size[1])
574 size[1] = gd->arch.resv_ram - base[1];
577 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
579 fsl_fdt_fixup_flash(blob);
581 #ifdef CONFIG_FSL_MC_ENET
582 fdt_fixup_board_enet(blob);
583 err = fsl_mc_ldpaa_exit(bd);
591 #endif /* defined(CONFIG_SPL_BUILD) */