2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
17 #include <fsl-mc/ldpaa_wriop.h>
19 #include "../common/qixis.h"
21 #include "ls2080aqds_qixis.h"
24 #ifdef CONFIG_FSL_MC_ENET
25 /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
26 * Bank 1 -> Lanes A, B, C, D, E, F, G, H
27 * Bank 2 -> Lanes A,B, C, D, E, F, G, H
30 /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
31 * means that the mapping must be determined dynamically, or that the lane
32 * maps to something other than a board slot.
35 static u8 lane_to_slot_fsm1[] = {
36 0, 0, 0, 0, 0, 0, 0, 0
39 static u8 lane_to_slot_fsm2[] = {
40 0, 0, 0, 0, 0, 0, 0, 0
43 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
47 static int xqsgii_riser_phy_addr[] = {
48 XQSGMII_CARD_PHY1_PORT0_ADDR,
49 XQSGMII_CARD_PHY2_PORT0_ADDR,
50 XQSGMII_CARD_PHY3_PORT0_ADDR,
51 XQSGMII_CARD_PHY4_PORT0_ADDR,
52 XQSGMII_CARD_PHY3_PORT2_ADDR,
53 XQSGMII_CARD_PHY1_PORT2_ADDR,
54 XQSGMII_CARD_PHY4_PORT2_ADDR,
55 XQSGMII_CARD_PHY2_PORT2_ADDR,
58 static int sgmii_riser_phy_addr[] = {
59 SGMII_CARD_PORT1_PHY_ADDR,
60 SGMII_CARD_PORT2_PHY_ADDR,
61 SGMII_CARD_PORT3_PHY_ADDR,
62 SGMII_CARD_PORT4_PHY_ADDR,
65 /* Slot2 does not have EMI connections */
66 #define EMI_NONE 0xFFFFFFFF
76 static const char * const mdio_names[] = {
83 DEFAULT_WRIOP_MDIO2_NAME,
86 struct ls2080a_qds_mdio {
88 struct mii_dev *realbus;
91 static void sgmii_configure_repeater(int serdes_port)
96 int dpmac_id = 0, dpmac, mii_bus = 0;
98 char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
99 uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
101 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
102 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
103 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
104 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
106 int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
108 /* Set I2c to Slot 1 */
109 i2c_write(0x77, 0, 0, &a, 1);
111 for (dpmac = 0; dpmac < 8; dpmac++) {
112 /* Check the PHY status */
113 switch (serdes_port) {
116 dpmac_id = dpmac + 1;
120 dpmac_id = dpmac + 9;
122 i2c_write(0x76, 0, 0, &a, 1);
126 ret = miiphy_set_current_dev(dev[mii_bus]);
130 bus = mdio_get_current_dev();
131 debug("Reading from bus %s\n", bus->name);
133 ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
139 ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
146 if ((value & 0xfff) == 0x40f) {
147 printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
151 for (i = 0; i < 4; i++) {
152 for (j = 0; j < 4; j++) {
154 i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
156 i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
158 i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
160 i2c_write(i2c_addr[dpmac], 0xf, 1,
162 i2c_write(i2c_addr[dpmac], 0x11, 1,
165 i2c_write(i2c_addr[dpmac], 0x16, 1,
167 i2c_write(i2c_addr[dpmac], 0x18, 1,
171 i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
173 i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
175 i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
177 ret = miiphy_read(dev[mii_bus],
178 riser_phy_addr[dpmac],
184 ret = miiphy_read(dev[mii_bus],
185 riser_phy_addr[dpmac],
191 if ((value & 0xfff) == 0x40f) {
192 printf("DPMAC %d :PHY is configured ",
194 printf("after setting repeater 0x%x\n",
199 printf("DPMAC %d :PHY is failed to ",
201 printf("configure the repeater 0x%x\n",
208 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
212 static void qsgmii_configure_repeater(int dpmac)
216 int i2c_phy_addr = 0;
218 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
220 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
221 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
222 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
223 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
225 const char *dev = "LS2080A_QDS_MDIO0";
227 unsigned short value;
229 /* Set I2c to Slot 1 */
230 i2c_write(0x77, 0, 0, &a, 1);
237 i2c_phy_addr = i2c_addr[0];
245 i2c_phy_addr = i2c_addr[1];
253 i2c_phy_addr = i2c_addr[2];
261 i2c_phy_addr = i2c_addr[3];
266 /* Check the PHY status */
267 ret = miiphy_set_current_dev(dev);
268 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
270 ret = miiphy_read(dev, phy_addr, 0x11, &value);
272 ret = miiphy_read(dev, phy_addr, 0x11, &value);
274 if ((value & 0xf) == 0xf) {
275 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
279 for (i = 0; i < 4; i++) {
280 for (j = 0; j < 4; j++) {
282 i2c_write(i2c_phy_addr, 6, 1, &a, 1);
284 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
286 i2c_write(i2c_phy_addr, 8, 1, &a, 1);
288 i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
289 i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
291 i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
292 i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
295 i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
297 i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
299 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
301 ret = miiphy_read(dev, phy_addr, 0x11, &value);
305 ret = miiphy_read(dev, phy_addr, 0x11, &value);
309 if ((value & 0xf) == 0xf) {
310 printf("DPMAC %d :PHY is ..... Configured\n",
317 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
321 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
323 return mdio_names[muxval];
326 struct mii_dev *mii_dev_for_muxval(u8 muxval)
329 const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
332 printf("No bus for muxval %x\n", muxval);
336 bus = miiphy_get_dev_by_name(name);
339 printf("No bus by name %s\n", name);
346 static void ls2080a_qds_enable_SFP_TX(u8 muxval)
350 brdcfg9 = QIXIS_READ(brdcfg[9]);
351 brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
352 brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
353 QIXIS_WRITE(brdcfg[9], brdcfg9);
356 static void ls2080a_qds_mux_mdio(u8 muxval)
361 brdcfg4 = QIXIS_READ(brdcfg[4]);
362 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
363 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
364 QIXIS_WRITE(brdcfg[4], brdcfg4);
368 static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
369 int devad, int regnum)
371 struct ls2080a_qds_mdio *priv = bus->priv;
373 ls2080a_qds_mux_mdio(priv->muxval);
375 return priv->realbus->read(priv->realbus, addr, devad, regnum);
378 static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
379 int regnum, u16 value)
381 struct ls2080a_qds_mdio *priv = bus->priv;
383 ls2080a_qds_mux_mdio(priv->muxval);
385 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
388 static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
390 struct ls2080a_qds_mdio *priv = bus->priv;
392 return priv->realbus->reset(priv->realbus);
395 static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
397 struct ls2080a_qds_mdio *pmdio;
398 struct mii_dev *bus = mdio_alloc();
401 printf("Failed to allocate ls2080a_qds MDIO bus\n");
405 pmdio = malloc(sizeof(*pmdio));
407 printf("Failed to allocate ls2080a_qds private data\n");
412 bus->read = ls2080a_qds_mdio_read;
413 bus->write = ls2080a_qds_mdio_write;
414 bus->reset = ls2080a_qds_mdio_reset;
415 strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
417 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
419 if (!pmdio->realbus) {
420 printf("No bus with name %s\n", realbusname);
426 pmdio->muxval = muxval;
429 return mdio_register(bus);
433 * Initialize the dpmac_info array.
436 static void initialize_dpmac_to_slot(void)
438 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
439 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
440 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
441 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
442 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
443 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
444 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
447 env_hwconfig = getenv("hwconfig");
449 switch (serdes1_prtcl) {
453 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
455 lane_to_slot_fsm1[0] = EMI1_SLOT1;
456 lane_to_slot_fsm1[1] = EMI1_SLOT1;
457 lane_to_slot_fsm1[2] = EMI1_SLOT1;
458 lane_to_slot_fsm1[3] = EMI1_SLOT1;
459 if (hwconfig_f("xqsgmii", env_hwconfig)) {
460 lane_to_slot_fsm1[4] = EMI1_SLOT1;
461 lane_to_slot_fsm1[5] = EMI1_SLOT1;
462 lane_to_slot_fsm1[6] = EMI1_SLOT1;
463 lane_to_slot_fsm1[7] = EMI1_SLOT1;
465 lane_to_slot_fsm1[4] = EMI1_SLOT2;
466 lane_to_slot_fsm1[5] = EMI1_SLOT2;
467 lane_to_slot_fsm1[6] = EMI1_SLOT2;
468 lane_to_slot_fsm1[7] = EMI1_SLOT2;
473 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
477 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
478 __func__, serdes1_prtcl);
482 switch (serdes2_prtcl) {
487 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
489 lane_to_slot_fsm2[0] = EMI1_SLOT4;
490 lane_to_slot_fsm2[1] = EMI1_SLOT4;
491 lane_to_slot_fsm2[2] = EMI1_SLOT4;
492 lane_to_slot_fsm2[3] = EMI1_SLOT4;
494 if (hwconfig_f("xqsgmii", env_hwconfig)) {
495 lane_to_slot_fsm2[4] = EMI1_SLOT4;
496 lane_to_slot_fsm2[5] = EMI1_SLOT4;
497 lane_to_slot_fsm2[6] = EMI1_SLOT4;
498 lane_to_slot_fsm2[7] = EMI1_SLOT4;
500 /* No MDIO physical connection */
501 lane_to_slot_fsm2[4] = EMI1_SLOT6;
502 lane_to_slot_fsm2[5] = EMI1_SLOT6;
503 lane_to_slot_fsm2[6] = EMI1_SLOT6;
504 lane_to_slot_fsm2[7] = EMI1_SLOT6;
508 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
509 __func__ , serdes2_prtcl);
514 void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
518 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
519 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
520 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
521 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
522 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
523 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
524 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
527 char *env_hwconfig = getenv("hwconfig");
529 if (hwconfig_f("xqsgmii", env_hwconfig))
530 riser_phy_addr = &xqsgii_riser_phy_addr[0];
532 riser_phy_addr = &sgmii_riser_phy_addr[0];
534 if (dpmac_id > WRIOP1_DPMAC9)
537 switch (serdes1_prtcl) {
540 lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id);
541 slot = lane_to_slot_fsm1[lane];
545 /* Slot housing a SGMII riser card? */
546 wriop_set_phy_address(dpmac_id,
547 riser_phy_addr[dpmac_id - 1]);
548 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
549 bus = mii_dev_for_muxval(EMI1_SLOT1);
550 wriop_set_mdio(dpmac_id, bus);
553 /* Slot housing a SGMII riser card? */
554 wriop_set_phy_address(dpmac_id,
555 riser_phy_addr[dpmac_id - 1]);
556 dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
557 bus = mii_dev_for_muxval(EMI1_SLOT2);
558 wriop_set_mdio(dpmac_id, bus);
571 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
572 __func__ , serdes1_prtcl);
577 switch (serdes2_prtcl) {
581 lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
583 slot = lane_to_slot_fsm2[lane];
591 /* Slot housing a SGMII riser card? */
592 wriop_set_phy_address(dpmac_id,
593 riser_phy_addr[dpmac_id - 9]);
594 dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
595 bus = mii_dev_for_muxval(EMI1_SLOT4);
596 wriop_set_mdio(dpmac_id, bus);
601 /* Slot housing a SGMII riser card? */
602 wriop_set_phy_address(dpmac_id,
603 riser_phy_addr[dpmac_id - 13]);
604 dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
605 bus = mii_dev_for_muxval(EMI1_SLOT6);
606 wriop_set_mdio(dpmac_id, bus);
611 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
612 __func__, serdes2_prtcl);
617 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
621 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
622 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
623 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
624 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
626 switch (serdes1_prtcl) {
633 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
639 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
645 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
651 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
655 slot = lane_to_slot_fsm1[lane];
659 /* Slot housing a QSGMII riser card? */
660 wriop_set_phy_address(dpmac_id, dpmac_id - 1);
661 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
662 bus = mii_dev_for_muxval(EMI1_SLOT1);
663 wriop_set_mdio(dpmac_id, bus);
676 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
681 qsgmii_configure_repeater(dpmac_id);
684 void ls2080a_handle_phy_interface_xsgmii(int i)
686 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
687 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
688 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
689 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
691 switch (serdes1_prtcl) {
694 * XFI does not need a PHY to work, but to avoid U-Boot use
695 * default PHY address which is zero to a MAC when it found
696 * a MAC has no PHY address, we give a PHY address to XFI
697 * MAC, and should not use a real XAUI PHY address, since
698 * MDIO can access it successfully, and then MDIO thinks
699 * the XAUI card is used for the XFI MAC, which will cause
702 wriop_set_phy_address(i, i + 4);
703 ls2080a_qds_enable_SFP_TX(SFP_TX);
707 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
714 int board_eth_init(bd_t *bis)
717 #ifdef CONFIG_FSL_MC_ENET
718 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
719 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
720 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
721 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
722 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
723 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
724 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
726 struct memac_mdio_info *memac_mdio0_info;
727 struct memac_mdio_info *memac_mdio1_info;
731 env_hwconfig = getenv("hwconfig");
733 initialize_dpmac_to_slot();
735 memac_mdio0_info = (struct memac_mdio_info *)malloc(
736 sizeof(struct memac_mdio_info));
737 memac_mdio0_info->regs =
738 (struct memac_mdio_controller *)
739 CONFIG_SYS_FSL_WRIOP1_MDIO1;
740 memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
742 /* Register the real MDIO1 bus */
743 fm_memac_mdio_init(bis, memac_mdio0_info);
745 memac_mdio1_info = (struct memac_mdio_info *)malloc(
746 sizeof(struct memac_mdio_info));
747 memac_mdio1_info->regs =
748 (struct memac_mdio_controller *)
749 CONFIG_SYS_FSL_WRIOP1_MDIO2;
750 memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
752 /* Register the real MDIO2 bus */
753 fm_memac_mdio_init(bis, memac_mdio1_info);
755 /* Register the muxing front-ends to the MDIO buses */
756 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
757 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
758 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
759 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
760 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
761 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
763 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
765 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
766 switch (wriop_get_enet_if(i)) {
767 case PHY_INTERFACE_MODE_QSGMII:
768 ls2080a_handle_phy_interface_qsgmii(i);
770 case PHY_INTERFACE_MODE_SGMII:
771 ls2080a_handle_phy_interface_sgmii(i);
773 case PHY_INTERFACE_MODE_XGMII:
774 ls2080a_handle_phy_interface_xsgmii(i);
784 error = cpu_eth_init(bis);
786 if (hwconfig_f("xqsgmii", env_hwconfig)) {
787 if (serdes1_prtcl == 0x7)
788 sgmii_configure_repeater(1);
789 if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
790 serdes2_prtcl == 0x49)
791 sgmii_configure_repeater(2);
794 error = pci_eth_init(bis);
798 #ifdef CONFIG_FSL_MC_ENET