2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
17 #include <fsl-mc/ldpaa_wriop.h>
19 #include "../common/qixis.h"
21 #include "ls2080aqds_qixis.h"
23 #define MC_BOOT_ENV_VAR "mcinitcmd"
25 #ifdef CONFIG_FSL_MC_ENET
26 /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
27 * Bank 1 -> Lanes A, B, C, D, E, F, G, H
28 * Bank 2 -> Lanes A,B, C, D, E, F, G, H
31 /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
32 * means that the mapping must be determined dynamically, or that the lane
33 * maps to something other than a board slot.
36 static u8 lane_to_slot_fsm1[] = {
37 0, 0, 0, 0, 0, 0, 0, 0
40 static u8 lane_to_slot_fsm2[] = {
41 0, 0, 0, 0, 0, 0, 0, 0
44 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
48 static int xqsgii_riser_phy_addr[] = {
49 XQSGMII_CARD_PHY1_PORT0_ADDR,
50 XQSGMII_CARD_PHY2_PORT0_ADDR,
51 XQSGMII_CARD_PHY3_PORT0_ADDR,
52 XQSGMII_CARD_PHY4_PORT0_ADDR,
53 XQSGMII_CARD_PHY3_PORT2_ADDR,
54 XQSGMII_CARD_PHY1_PORT2_ADDR,
55 XQSGMII_CARD_PHY4_PORT2_ADDR,
56 XQSGMII_CARD_PHY2_PORT2_ADDR,
59 static int sgmii_riser_phy_addr[] = {
60 SGMII_CARD_PORT1_PHY_ADDR,
61 SGMII_CARD_PORT2_PHY_ADDR,
62 SGMII_CARD_PORT3_PHY_ADDR,
63 SGMII_CARD_PORT4_PHY_ADDR,
66 /* Slot2 does not have EMI connections */
77 static const char * const mdio_names[] = {
84 DEFAULT_WRIOP_MDIO2_NAME,
87 struct ls2080a_qds_mdio {
89 struct mii_dev *realbus;
92 static void sgmii_configure_repeater(int serdes_port)
97 int dpmac_id = 0, dpmac, mii_bus = 0;
99 char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
100 uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
102 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
103 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
104 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
105 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
107 int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
109 /* Set I2c to Slot 1 */
110 i2c_write(0x77, 0, 0, &a, 1);
112 for (dpmac = 0; dpmac < 8; dpmac++) {
113 /* Check the PHY status */
114 switch (serdes_port) {
117 dpmac_id = dpmac + 1;
121 dpmac_id = dpmac + 9;
123 i2c_write(0x76, 0, 0, &a, 1);
127 ret = miiphy_set_current_dev(dev[mii_bus]);
131 bus = mdio_get_current_dev();
132 debug("Reading from bus %s\n", bus->name);
134 ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
140 ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
147 if ((value & 0xfff) == 0x40f) {
148 printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
152 for (i = 0; i < 4; i++) {
153 for (j = 0; j < 4; j++) {
155 i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
157 i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
159 i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
161 i2c_write(i2c_addr[dpmac], 0xf, 1,
163 i2c_write(i2c_addr[dpmac], 0x11, 1,
166 i2c_write(i2c_addr[dpmac], 0x16, 1,
168 i2c_write(i2c_addr[dpmac], 0x18, 1,
172 i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
174 i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
176 i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
178 ret = miiphy_read(dev[mii_bus],
179 riser_phy_addr[dpmac],
185 ret = miiphy_read(dev[mii_bus],
186 riser_phy_addr[dpmac],
192 if ((value & 0xfff) == 0x40f) {
193 printf("DPMAC %d :PHY is configured ",
195 printf("after setting repeater 0x%x\n",
200 printf("DPMAC %d :PHY is failed to ",
202 printf("configure the repeater 0x%x\n",
209 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
213 static void qsgmii_configure_repeater(int dpmac)
217 int i2c_phy_addr = 0;
219 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
221 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
222 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
223 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
224 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
226 const char *dev = "LS2080A_QDS_MDIO0";
228 unsigned short value;
230 /* Set I2c to Slot 1 */
231 i2c_write(0x77, 0, 0, &a, 1);
238 i2c_phy_addr = i2c_addr[0];
246 i2c_phy_addr = i2c_addr[1];
254 i2c_phy_addr = i2c_addr[2];
262 i2c_phy_addr = i2c_addr[3];
267 /* Check the PHY status */
268 ret = miiphy_set_current_dev(dev);
269 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
271 ret = miiphy_read(dev, phy_addr, 0x11, &value);
273 ret = miiphy_read(dev, phy_addr, 0x11, &value);
275 if ((value & 0xf) == 0xf) {
276 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
280 for (i = 0; i < 4; i++) {
281 for (j = 0; j < 4; j++) {
283 i2c_write(i2c_phy_addr, 6, 1, &a, 1);
285 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
287 i2c_write(i2c_phy_addr, 8, 1, &a, 1);
289 i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
290 i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
292 i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
293 i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
296 i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
298 i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
300 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
302 ret = miiphy_read(dev, phy_addr, 0x11, &value);
306 ret = miiphy_read(dev, phy_addr, 0x11, &value);
310 if ((value & 0xf) == 0xf) {
311 printf("DPMAC %d :PHY is ..... Configured\n",
318 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
322 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
324 return mdio_names[muxval];
327 struct mii_dev *mii_dev_for_muxval(u8 muxval)
330 const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
333 printf("No bus for muxval %x\n", muxval);
337 bus = miiphy_get_dev_by_name(name);
340 printf("No bus by name %s\n", name);
347 static void ls2080a_qds_enable_SFP_TX(u8 muxval)
351 brdcfg9 = QIXIS_READ(brdcfg[9]);
352 brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
353 brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
354 QIXIS_WRITE(brdcfg[9], brdcfg9);
357 static void ls2080a_qds_mux_mdio(u8 muxval)
362 brdcfg4 = QIXIS_READ(brdcfg[4]);
363 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
364 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
365 QIXIS_WRITE(brdcfg[4], brdcfg4);
369 static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
370 int devad, int regnum)
372 struct ls2080a_qds_mdio *priv = bus->priv;
374 ls2080a_qds_mux_mdio(priv->muxval);
376 return priv->realbus->read(priv->realbus, addr, devad, regnum);
379 static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
380 int regnum, u16 value)
382 struct ls2080a_qds_mdio *priv = bus->priv;
384 ls2080a_qds_mux_mdio(priv->muxval);
386 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
389 static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
391 struct ls2080a_qds_mdio *priv = bus->priv;
393 return priv->realbus->reset(priv->realbus);
396 static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
398 struct ls2080a_qds_mdio *pmdio;
399 struct mii_dev *bus = mdio_alloc();
402 printf("Failed to allocate ls2080a_qds MDIO bus\n");
406 pmdio = malloc(sizeof(*pmdio));
408 printf("Failed to allocate ls2080a_qds private data\n");
413 bus->read = ls2080a_qds_mdio_read;
414 bus->write = ls2080a_qds_mdio_write;
415 bus->reset = ls2080a_qds_mdio_reset;
416 strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
418 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
420 if (!pmdio->realbus) {
421 printf("No bus with name %s\n", realbusname);
427 pmdio->muxval = muxval;
430 return mdio_register(bus);
434 * Initialize the dpmac_info array.
437 static void initialize_dpmac_to_slot(void)
439 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
440 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
441 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
442 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
443 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
444 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
445 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
448 env_hwconfig = getenv("hwconfig");
450 switch (serdes1_prtcl) {
454 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
456 lane_to_slot_fsm1[0] = EMI1_SLOT1;
457 lane_to_slot_fsm1[1] = EMI1_SLOT1;
458 lane_to_slot_fsm1[2] = EMI1_SLOT1;
459 lane_to_slot_fsm1[3] = EMI1_SLOT1;
460 if (hwconfig_f("xqsgmii", env_hwconfig)) {
461 lane_to_slot_fsm1[4] = EMI1_SLOT1;
462 lane_to_slot_fsm1[5] = EMI1_SLOT1;
463 lane_to_slot_fsm1[6] = EMI1_SLOT1;
464 lane_to_slot_fsm1[7] = EMI1_SLOT1;
466 lane_to_slot_fsm1[4] = EMI1_SLOT2;
467 lane_to_slot_fsm1[5] = EMI1_SLOT2;
468 lane_to_slot_fsm1[6] = EMI1_SLOT2;
469 lane_to_slot_fsm1[7] = EMI1_SLOT2;
474 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
476 if (hwconfig_f("xqsgmii", env_hwconfig)) {
477 lane_to_slot_fsm1[0] = EMI1_SLOT3;
478 lane_to_slot_fsm1[1] = EMI1_SLOT3;
479 lane_to_slot_fsm1[2] = EMI1_SLOT3;
480 lane_to_slot_fsm1[3] = EMI_NONE;
482 lane_to_slot_fsm1[0] = EMI_NONE;
483 lane_to_slot_fsm1[1] = EMI_NONE;
484 lane_to_slot_fsm1[2] = EMI_NONE;
485 lane_to_slot_fsm1[3] = EMI_NONE;
487 lane_to_slot_fsm1[4] = EMI1_SLOT3;
488 lane_to_slot_fsm1[5] = EMI1_SLOT3;
489 lane_to_slot_fsm1[6] = EMI1_SLOT3;
490 lane_to_slot_fsm1[7] = EMI_NONE;
494 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
496 if (hwconfig_f("xqsgmii", env_hwconfig)) {
497 lane_to_slot_fsm1[0] = EMI1_SLOT3;
498 lane_to_slot_fsm1[1] = EMI1_SLOT3;
499 lane_to_slot_fsm1[2] = EMI_NONE;
500 lane_to_slot_fsm1[3] = EMI_NONE;
502 lane_to_slot_fsm1[0] = EMI_NONE;
503 lane_to_slot_fsm1[1] = EMI_NONE;
504 lane_to_slot_fsm1[2] = EMI_NONE;
505 lane_to_slot_fsm1[3] = EMI_NONE;
507 lane_to_slot_fsm1[4] = EMI1_SLOT3;
508 lane_to_slot_fsm1[5] = EMI1_SLOT3;
509 lane_to_slot_fsm1[6] = EMI_NONE;
510 lane_to_slot_fsm1[7] = EMI_NONE;
516 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
520 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
521 __func__, serdes1_prtcl);
525 switch (serdes2_prtcl) {
530 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
532 lane_to_slot_fsm2[0] = EMI1_SLOT4;
533 lane_to_slot_fsm2[1] = EMI1_SLOT4;
534 lane_to_slot_fsm2[2] = EMI1_SLOT4;
535 lane_to_slot_fsm2[3] = EMI1_SLOT4;
537 if (hwconfig_f("xqsgmii", env_hwconfig)) {
538 lane_to_slot_fsm2[4] = EMI1_SLOT4;
539 lane_to_slot_fsm2[5] = EMI1_SLOT4;
540 lane_to_slot_fsm2[6] = EMI1_SLOT4;
541 lane_to_slot_fsm2[7] = EMI1_SLOT4;
543 /* No MDIO physical connection */
544 lane_to_slot_fsm2[4] = EMI1_SLOT6;
545 lane_to_slot_fsm2[5] = EMI1_SLOT6;
546 lane_to_slot_fsm2[6] = EMI1_SLOT6;
547 lane_to_slot_fsm2[7] = EMI1_SLOT6;
552 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
554 lane_to_slot_fsm2[0] = EMI_NONE;
555 lane_to_slot_fsm2[1] = EMI1_SLOT5;
556 lane_to_slot_fsm2[2] = EMI1_SLOT5;
557 lane_to_slot_fsm2[3] = EMI1_SLOT5;
559 if (hwconfig_f("xqsgmii", env_hwconfig)) {
560 lane_to_slot_fsm2[4] = EMI_NONE;
561 lane_to_slot_fsm2[5] = EMI1_SLOT5;
562 lane_to_slot_fsm2[6] = EMI1_SLOT5;
563 lane_to_slot_fsm2[7] = EMI1_SLOT5;
568 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
570 if (hwconfig_f("xqsgmii", env_hwconfig)) {
571 lane_to_slot_fsm2[0] = EMI_NONE;
572 lane_to_slot_fsm2[1] = EMI_NONE;
573 lane_to_slot_fsm2[2] = EMI_NONE;
574 lane_to_slot_fsm2[3] = EMI_NONE;
576 lane_to_slot_fsm2[4] = EMI_NONE;
577 lane_to_slot_fsm2[5] = EMI_NONE;
578 lane_to_slot_fsm2[6] = EMI1_SLOT5;
579 lane_to_slot_fsm2[7] = EMI1_SLOT5;
583 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
584 __func__ , serdes2_prtcl);
589 void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
593 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
594 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
595 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
596 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
597 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
598 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
599 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
602 char *env_hwconfig = getenv("hwconfig");
604 if (hwconfig_f("xqsgmii", env_hwconfig))
605 riser_phy_addr = &xqsgii_riser_phy_addr[0];
607 riser_phy_addr = &sgmii_riser_phy_addr[0];
609 if (dpmac_id > WRIOP1_DPMAC9)
612 switch (serdes1_prtcl) {
616 lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
618 slot = lane_to_slot_fsm1[lane];
622 /* Slot housing a SGMII riser card? */
623 wriop_set_phy_address(dpmac_id,
624 riser_phy_addr[dpmac_id - 1]);
625 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
626 bus = mii_dev_for_muxval(EMI1_SLOT1);
627 wriop_set_mdio(dpmac_id, bus);
630 /* Slot housing a SGMII riser card? */
631 wriop_set_phy_address(dpmac_id,
632 riser_phy_addr[dpmac_id - 1]);
633 dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
634 bus = mii_dev_for_muxval(EMI1_SLOT2);
635 wriop_set_mdio(dpmac_id, bus);
638 if (slot == EMI_NONE)
640 if (serdes1_prtcl == 0x39) {
641 wriop_set_phy_address(dpmac_id,
642 riser_phy_addr[dpmac_id - 2]);
643 if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
645 wriop_set_phy_address(dpmac_id,
646 riser_phy_addr[dpmac_id - 3]);
648 wriop_set_phy_address(dpmac_id,
649 riser_phy_addr[dpmac_id - 2]);
650 if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
652 wriop_set_phy_address(dpmac_id,
653 riser_phy_addr[dpmac_id - 3]);
655 dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
656 bus = mii_dev_for_muxval(EMI1_SLOT3);
657 wriop_set_mdio(dpmac_id, bus);
668 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
669 __func__ , serdes1_prtcl);
674 switch (serdes2_prtcl) {
680 lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
682 slot = lane_to_slot_fsm2[lane];
690 /* Slot housing a SGMII riser card? */
691 wriop_set_phy_address(dpmac_id,
692 riser_phy_addr[dpmac_id - 9]);
693 dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
694 bus = mii_dev_for_muxval(EMI1_SLOT4);
695 wriop_set_mdio(dpmac_id, bus);
698 if (slot == EMI_NONE)
700 if (serdes2_prtcl == 0x47) {
701 wriop_set_phy_address(dpmac_id,
702 riser_phy_addr[dpmac_id - 10]);
703 if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
705 wriop_set_phy_address(dpmac_id,
706 riser_phy_addr[dpmac_id - 11]);
708 wriop_set_phy_address(dpmac_id,
709 riser_phy_addr[dpmac_id - 11]);
711 dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
712 bus = mii_dev_for_muxval(EMI1_SLOT5);
713 wriop_set_mdio(dpmac_id, bus);
716 /* Slot housing a SGMII riser card? */
717 wriop_set_phy_address(dpmac_id,
718 riser_phy_addr[dpmac_id - 13]);
719 dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
720 bus = mii_dev_for_muxval(EMI1_SLOT6);
721 wriop_set_mdio(dpmac_id, bus);
726 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
727 __func__, serdes2_prtcl);
732 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
736 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
737 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
738 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
739 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
741 switch (serdes1_prtcl) {
748 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
754 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
760 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
766 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
770 slot = lane_to_slot_fsm1[lane];
774 /* Slot housing a QSGMII riser card? */
775 wriop_set_phy_address(dpmac_id, dpmac_id - 1);
776 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
777 bus = mii_dev_for_muxval(EMI1_SLOT1);
778 wriop_set_mdio(dpmac_id, bus);
791 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
796 qsgmii_configure_repeater(dpmac_id);
799 void ls2080a_handle_phy_interface_xsgmii(int i)
801 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
802 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
803 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
804 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
806 switch (serdes1_prtcl) {
811 * XFI does not need a PHY to work, but to avoid U-Boot use
812 * default PHY address which is zero to a MAC when it found
813 * a MAC has no PHY address, we give a PHY address to XFI
814 * MAC, and should not use a real XAUI PHY address, since
815 * MDIO can access it successfully, and then MDIO thinks
816 * the XAUI card is used for the XFI MAC, which will cause
819 wriop_set_phy_address(i, i + 4);
820 ls2080a_qds_enable_SFP_TX(SFP_TX);
824 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
831 int board_eth_init(bd_t *bis)
834 char *mc_boot_env_var;
835 #ifdef CONFIG_FSL_MC_ENET
836 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
837 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
838 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
839 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
840 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
841 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
842 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
844 struct memac_mdio_info *memac_mdio0_info;
845 struct memac_mdio_info *memac_mdio1_info;
849 env_hwconfig = getenv("hwconfig");
851 initialize_dpmac_to_slot();
853 memac_mdio0_info = (struct memac_mdio_info *)malloc(
854 sizeof(struct memac_mdio_info));
855 memac_mdio0_info->regs =
856 (struct memac_mdio_controller *)
857 CONFIG_SYS_FSL_WRIOP1_MDIO1;
858 memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
860 /* Register the real MDIO1 bus */
861 fm_memac_mdio_init(bis, memac_mdio0_info);
863 memac_mdio1_info = (struct memac_mdio_info *)malloc(
864 sizeof(struct memac_mdio_info));
865 memac_mdio1_info->regs =
866 (struct memac_mdio_controller *)
867 CONFIG_SYS_FSL_WRIOP1_MDIO2;
868 memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
870 /* Register the real MDIO2 bus */
871 fm_memac_mdio_init(bis, memac_mdio1_info);
873 /* Register the muxing front-ends to the MDIO buses */
874 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
875 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
876 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
877 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
878 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
879 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
881 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
883 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
884 switch (wriop_get_enet_if(i)) {
885 case PHY_INTERFACE_MODE_QSGMII:
886 ls2080a_handle_phy_interface_qsgmii(i);
888 case PHY_INTERFACE_MODE_SGMII:
889 ls2080a_handle_phy_interface_sgmii(i);
891 case PHY_INTERFACE_MODE_XGMII:
892 ls2080a_handle_phy_interface_xsgmii(i);
902 mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
904 run_command_list(mc_boot_env_var, -1, 0);
905 error = cpu_eth_init(bis);
907 if (hwconfig_f("xqsgmii", env_hwconfig)) {
908 if (serdes1_prtcl == 0x7)
909 sgmii_configure_repeater(1);
910 if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
911 serdes2_prtcl == 0x49)
912 sgmii_configure_repeater(2);
915 error = pci_eth_init(bis);
919 #ifdef CONFIG_FSL_MC_ENET