2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <fdt_support.h>
15 #include <fsl_debug_server.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <environment.h>
20 #include <asm/arch/soc.h>
23 #include "../common/qixis.h"
24 #include "ls2080aqds_qixis.h"
26 #define PIN_MUX_SEL_SDHC 0x00
27 #define PIN_MUX_SEL_DSPI 0x0a
29 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
31 DECLARE_GLOBAL_DATA_PTR;
38 unsigned long long get_qixis_addr(void)
40 unsigned long long addr;
42 if (gd->flags & GD_FLG_RELOC)
43 addr = QIXIS_BASE_PHYS;
45 addr = QIXIS_BASE_PHYS_EARLY;
48 * IFC address under 256MB is mapped to 0x30000000, any address above
49 * is mapped to 0x5_10000000 up to 4GB.
51 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
60 static const char *const freq[] = {"100", "125", "156.25",
65 printf("Board: %s-QDS, ", buf);
67 sw = QIXIS_READ(arch);
68 printf("Board Arch: V%d, ", sw >> 4);
69 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
71 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
73 sw = QIXIS_READ(brdcfg[0]);
74 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
77 printf("vBank: %d\n", sw);
85 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
87 printf("FPGA: v%d (%s), build %d",
88 (int)QIXIS_READ(scver), qixis_read_tag(buf),
89 (int)qixis_read_minor());
90 /* the timestamp string contains "\n" at the end */
91 printf(" on %s", qixis_read_time(buf));
94 * Display the actual SERDES reference clocks as configured by the
95 * dip switches on the board. Note that the SWx registers could
96 * technically be set to force the reference clocks to match the
97 * values that the SERDES expects (or vice versa). For now, however,
98 * we just display both values and hope the user notices when they
101 puts("SERDES1 Reference : ");
102 sw = QIXIS_READ(brdcfg[2]);
103 clock = (sw >> 6) & 3;
104 printf("Clock1 = %sMHz ", freq[clock]);
105 clock = (sw >> 4) & 3;
106 printf("Clock2 = %sMHz", freq[clock]);
108 puts("\nSERDES2 Reference : ");
109 clock = (sw >> 2) & 3;
110 printf("Clock1 = %sMHz ", freq[clock]);
111 clock = (sw >> 0) & 3;
112 printf("Clock2 = %sMHz\n", freq[clock]);
117 unsigned long get_board_sys_clk(void)
119 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
121 switch (sysclk_conf & 0x0F) {
122 case QIXIS_SYSCLK_83:
124 case QIXIS_SYSCLK_100:
126 case QIXIS_SYSCLK_125:
128 case QIXIS_SYSCLK_133:
130 case QIXIS_SYSCLK_150:
132 case QIXIS_SYSCLK_160:
134 case QIXIS_SYSCLK_166:
140 unsigned long get_board_ddr_clk(void)
142 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
144 switch ((ddrclk_conf & 0x30) >> 4) {
145 case QIXIS_DDRCLK_100:
147 case QIXIS_DDRCLK_125:
149 case QIXIS_DDRCLK_133:
155 int select_i2c_ch_pca9547(u8 ch)
159 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
161 puts("PCA: failed to select proper channel\n");
168 int config_board_mux(int ctrl_type)
172 reg5 = QIXIS_READ(brdcfg[5]);
176 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
179 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
182 printf("Wrong mux interface type\n");
186 QIXIS_WRITE(brdcfg[5], reg5);
194 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
197 init_final_memctl_regs();
199 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
201 env_hwconfig = getenv("hwconfig");
203 if (hwconfig_f("dspi", env_hwconfig) &&
204 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
205 config_board_mux(MUX_TYPE_DSPI);
207 config_board_mux(MUX_TYPE_SDHC);
209 #ifdef CONFIG_ENV_IS_NOWHERE
210 gd->env_addr = (ulong)&default_environment[0];
212 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
213 rtc_enable_32khz_output();
218 int board_early_init_f(void)
220 fsl_lsch3_early_init_f();
224 void detail_board_ddr_info(void)
227 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
229 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
230 if (gd->bd->bi_dram[2].size) {
232 print_size(gd->bd->bi_dram[2].size, "");
233 print_ddr_info(CONFIG_DP_DDR_CTRL);
240 gd->ram_size = initdram(0);
245 #if defined(CONFIG_ARCH_MISC_INIT)
246 int arch_misc_init(void)
248 #ifdef CONFIG_FSL_DEBUG_SERVER
256 unsigned long get_dram_size_to_hide(void)
258 unsigned long dram_to_hide = 0;
260 /* Carve the Debug Server private DRAM block from the end of DRAM */
261 #ifdef CONFIG_FSL_DEBUG_SERVER
262 dram_to_hide += debug_server_get_dram_block_size();
265 /* Carve the MC private DRAM block from the end of DRAM */
266 #ifdef CONFIG_FSL_MC_ENET
267 dram_to_hide += mc_get_dram_block_size();
270 return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
273 #ifdef CONFIG_FSL_MC_ENET
274 void fdt_fixup_board_enet(void *fdt)
278 offset = fdt_path_offset(fdt, "/fsl-mc");
281 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
284 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
289 if (get_mc_boot_status() == 0)
290 fdt_status_okay(fdt, offset);
292 fdt_status_fail(fdt, offset);
296 #ifdef CONFIG_OF_BOARD_SETUP
297 int ft_board_setup(void *blob, bd_t *bd)
300 u64 base[CONFIG_NR_DRAM_BANKS];
301 u64 size[CONFIG_NR_DRAM_BANKS];
303 ft_cpu_setup(blob, bd);
305 /* fixup DT for the two GPP DDR banks */
306 base[0] = gd->bd->bi_dram[0].start;
307 size[0] = gd->bd->bi_dram[0].size;
308 base[1] = gd->bd->bi_dram[1].start;
309 size[1] = gd->bd->bi_dram[1].size;
311 fdt_fixup_memory_banks(blob, base, size, 2);
313 #ifdef CONFIG_FSL_MC_ENET
314 fdt_fixup_board_enet(blob);
315 err = fsl_mc_ldpaa_exit(bd);
324 void qixis_dump_switch(void)
328 QIXIS_WRITE(cms[0], 0x00);
329 nr_of_cfgsw = QIXIS_READ(cms[1]);
331 puts("DIP switch settings dump:\n");
332 for (i = 1; i <= nr_of_cfgsw; i++) {
333 QIXIS_WRITE(cms[0], i);
334 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));