2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
14 #include <fdt_support.h>
16 #include <fsl_debug_server.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h>
20 #include <asm/arch/soc.h>
23 #include "../common/qixis.h"
24 #include "ls2080ardb_qixis.h"
25 #include "../common/vid.h"
27 #define PIN_MUX_SEL_SDHC 0x00
28 #define PIN_MUX_SEL_DSPI 0x0a
30 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
31 DECLARE_GLOBAL_DATA_PTR;
38 unsigned long long get_qixis_addr(void)
40 unsigned long long addr;
42 if (gd->flags & GD_FLG_RELOC)
43 addr = QIXIS_BASE_PHYS;
45 addr = QIXIS_BASE_PHYS_EARLY;
48 * IFC address under 256MB is mapped to 0x30000000, any address above
49 * is mapped to 0x5_10000000 up to 4GB.
51 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
62 printf("Board: %s-RDB, ", buf);
64 sw = QIXIS_READ(arch);
65 printf("Board Arch: V%d, ", sw >> 4);
66 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
68 sw = QIXIS_READ(brdcfg[0]);
69 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
72 printf("vBank: %d\n", sw);
76 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
78 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
80 puts("SERDES1 Reference : ");
81 printf("Clock1 = 156.25MHz ");
82 printf("Clock2 = 156.25MHz");
84 puts("\nSERDES2 Reference : ");
85 printf("Clock1 = 100MHz ");
86 printf("Clock2 = 100MHz\n");
91 unsigned long get_board_sys_clk(void)
93 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
95 switch (sysclk_conf & 0x0F) {
98 case QIXIS_SYSCLK_100:
100 case QIXIS_SYSCLK_125:
102 case QIXIS_SYSCLK_133:
104 case QIXIS_SYSCLK_150:
106 case QIXIS_SYSCLK_160:
108 case QIXIS_SYSCLK_166:
114 int select_i2c_ch_pca9547(u8 ch)
118 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
120 puts("PCA: failed to select proper channel\n");
127 int i2c_multiplexer_select_vid_channel(u8 channel)
129 return select_i2c_ch_pca9547(channel);
132 int config_board_mux(int ctrl_type)
136 reg5 = QIXIS_READ(brdcfg[5]);
140 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
143 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
146 printf("Wrong mux interface type\n");
150 QIXIS_WRITE(brdcfg[5], reg5);
158 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
159 #ifdef CONFIG_FSL_MC_ENET
160 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
164 init_final_memctl_regs();
166 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
168 env_hwconfig = getenv("hwconfig");
170 if (hwconfig_f("dspi", env_hwconfig) &&
171 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
172 config_board_mux(MUX_TYPE_DSPI);
174 config_board_mux(MUX_TYPE_SDHC);
176 #ifdef CONFIG_ENV_IS_NOWHERE
177 gd->env_addr = (ulong)&default_environment[0];
179 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
181 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
183 #ifdef CONFIG_FSL_MC_ENET
184 /* invert AQR405 IRQ pins polarity */
185 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
191 int board_early_init_f(void)
193 fsl_lsch3_early_init_f();
197 int misc_init_r(void)
199 if (hwconfig("sdhc"))
200 config_board_mux(MUX_TYPE_SDHC);
203 printf("Warning: Adjusting core voltage failed.\n");
208 void detail_board_ddr_info(void)
211 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
213 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
214 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
216 print_size(gd->bd->bi_dram[2].size, "");
217 print_ddr_info(CONFIG_DP_DDR_CTRL);
224 gd->ram_size = initdram(0);
229 #if defined(CONFIG_ARCH_MISC_INIT)
230 int arch_misc_init(void)
232 #ifdef CONFIG_FSL_DEBUG_SERVER
235 #ifdef CONFIG_FSL_CAAM
242 #ifdef CONFIG_FSL_MC_ENET
243 void fdt_fixup_board_enet(void *fdt)
247 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
250 offset = fdt_path_offset(fdt, "/fsl-mc");
253 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
258 if (get_mc_boot_status() == 0)
259 fdt_status_okay(fdt, offset);
261 fdt_status_fail(fdt, offset);
265 #ifdef CONFIG_OF_BOARD_SETUP
266 int ft_board_setup(void *blob, bd_t *bd)
268 #ifdef CONFIG_FSL_MC_ENET
271 u64 base[CONFIG_NR_DRAM_BANKS];
272 u64 size[CONFIG_NR_DRAM_BANKS];
274 ft_cpu_setup(blob, bd);
276 /* fixup DT for the two GPP DDR banks */
277 base[0] = gd->bd->bi_dram[0].start;
278 size[0] = gd->bd->bi_dram[0].size;
279 base[1] = gd->bd->bi_dram[1].start;
280 size[1] = gd->bd->bi_dram[1].size;
282 fdt_fixup_memory_banks(blob, base, size, 2);
284 #ifdef CONFIG_FSL_MC_ENET
285 fdt_fixup_board_enet(blob);
286 err = fsl_mc_ldpaa_exit(bd);
295 void qixis_dump_switch(void)
299 QIXIS_WRITE(cms[0], 0x00);
300 nr_of_cfgsw = QIXIS_READ(cms[1]);
302 puts("DIP switch settings dump:\n");
303 for (i = 1; i <= nr_of_cfgsw; i++) {
304 QIXIS_WRITE(cms[0], i);
305 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
310 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
311 * Both slots has 0x54, resulting 2nd slot unusable.
313 void update_spd_address(unsigned int ctrl_num,
319 sw = QIXIS_READ(arch);
320 if ((sw & 0xf) < 0x3) {
321 if (ctrl_num == 1 && slot == 0)
322 *addr = SPD_EEPROM_ADDRESS4;
323 else if (ctrl_num == 1 && slot == 1)
324 *addr = SPD_EEPROM_ADDRESS3;