2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
14 #include <fdt_support.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <environment.h>
18 #include <efi_loader.h>
20 #include <asm/arch/mmu.h>
21 #include <asm/arch/soc.h>
22 #include <asm/arch/ppa.h>
25 #include "../common/qixis.h"
26 #include "ls2080ardb_qixis.h"
27 #include "../common/vid.h"
29 #define PIN_MUX_SEL_SDHC 0x00
30 #define PIN_MUX_SEL_DSPI 0x0a
32 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
33 DECLARE_GLOBAL_DATA_PTR;
40 unsigned long long get_qixis_addr(void)
42 unsigned long long addr;
44 if (gd->flags & GD_FLG_RELOC)
45 addr = QIXIS_BASE_PHYS;
47 addr = QIXIS_BASE_PHYS_EARLY;
50 * IFC address under 256MB is mapped to 0x30000000, any address above
51 * is mapped to 0x5_10000000 up to 4GB.
53 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
64 printf("Board: %s-RDB, ", buf);
66 sw = QIXIS_READ(arch);
67 printf("Board Arch: V%d, ", sw >> 4);
68 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
70 sw = QIXIS_READ(brdcfg[0]);
71 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
74 printf("vBank: %d\n", sw);
78 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
80 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
82 puts("SERDES1 Reference : ");
83 printf("Clock1 = 156.25MHz ");
84 printf("Clock2 = 156.25MHz");
86 puts("\nSERDES2 Reference : ");
87 printf("Clock1 = 100MHz ");
88 printf("Clock2 = 100MHz\n");
93 unsigned long get_board_sys_clk(void)
95 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
97 switch (sysclk_conf & 0x0F) {
100 case QIXIS_SYSCLK_100:
102 case QIXIS_SYSCLK_125:
104 case QIXIS_SYSCLK_133:
106 case QIXIS_SYSCLK_150:
108 case QIXIS_SYSCLK_160:
110 case QIXIS_SYSCLK_166:
116 int select_i2c_ch_pca9547(u8 ch)
120 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
122 puts("PCA: failed to select proper channel\n");
129 int i2c_multiplexer_select_vid_channel(u8 channel)
131 return select_i2c_ch_pca9547(channel);
134 int config_board_mux(int ctrl_type)
138 reg5 = QIXIS_READ(brdcfg[5]);
142 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
145 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
148 printf("Wrong mux interface type\n");
152 QIXIS_WRITE(brdcfg[5], reg5);
160 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
161 #ifdef CONFIG_FSL_MC_ENET
162 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
166 init_final_memctl_regs();
168 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
170 env_hwconfig = getenv("hwconfig");
172 if (hwconfig_f("dspi", env_hwconfig) &&
173 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
174 config_board_mux(MUX_TYPE_DSPI);
176 config_board_mux(MUX_TYPE_SDHC);
178 #ifdef CONFIG_ENV_IS_NOWHERE
179 gd->env_addr = (ulong)&default_environment[0];
181 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
183 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
185 #ifdef CONFIG_FSL_LS_PPA
189 #ifdef CONFIG_FSL_MC_ENET
190 /* invert AQR405 IRQ pins polarity */
191 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
193 #ifdef CONFIG_FSL_CAAM
200 int board_early_init_f(void)
202 fsl_lsch3_early_init_f();
206 int misc_init_r(void)
208 if (hwconfig("sdhc"))
209 config_board_mux(MUX_TYPE_SDHC);
212 printf("Warning: Adjusting core voltage failed.\n");
217 void detail_board_ddr_info(void)
220 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
222 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
223 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
225 print_size(gd->bd->bi_dram[2].size, "");
226 print_ddr_info(CONFIG_DP_DDR_CTRL);
231 #if defined(CONFIG_ARCH_MISC_INIT)
232 int arch_misc_init(void)
238 #ifdef CONFIG_FSL_MC_ENET
239 void fdt_fixup_board_enet(void *fdt)
243 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
246 offset = fdt_path_offset(fdt, "/fsl-mc");
249 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
254 if (get_mc_boot_status() == 0)
255 fdt_status_okay(fdt, offset);
257 fdt_status_fail(fdt, offset);
260 void board_quiesce_devices(void)
262 fsl_mc_ldpaa_exit(gd->bd);
266 #ifdef CONFIG_OF_BOARD_SETUP
267 int ft_board_setup(void *blob, bd_t *bd)
269 u64 base[CONFIG_NR_DRAM_BANKS];
270 u64 size[CONFIG_NR_DRAM_BANKS];
272 ft_cpu_setup(blob, bd);
274 /* fixup DT for the two GPP DDR banks */
275 base[0] = gd->bd->bi_dram[0].start;
276 size[0] = gd->bd->bi_dram[0].size;
277 base[1] = gd->bd->bi_dram[1].start;
278 size[1] = gd->bd->bi_dram[1].size;
280 #ifdef CONFIG_RESV_RAM
281 /* reduce size if reserved memory is within this bank */
282 if (gd->arch.resv_ram >= base[0] &&
283 gd->arch.resv_ram < base[0] + size[0])
284 size[0] = gd->arch.resv_ram - base[0];
285 else if (gd->arch.resv_ram >= base[1] &&
286 gd->arch.resv_ram < base[1] + size[1])
287 size[1] = gd->arch.resv_ram - base[1];
290 fdt_fixup_memory_banks(blob, base, size, 2);
292 fsl_fdt_fixup_dr_usb(blob, bd);
294 #ifdef CONFIG_FSL_MC_ENET
295 fdt_fixup_board_enet(blob);
302 void qixis_dump_switch(void)
306 QIXIS_WRITE(cms[0], 0x00);
307 nr_of_cfgsw = QIXIS_READ(cms[1]);
309 puts("DIP switch settings dump:\n");
310 for (i = 1; i <= nr_of_cfgsw; i++) {
311 QIXIS_WRITE(cms[0], i);
312 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
317 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
318 * Both slots has 0x54, resulting 2nd slot unusable.
320 void update_spd_address(unsigned int ctrl_num,
326 sw = QIXIS_READ(arch);
327 if ((sw & 0xf) < 0x3) {
328 if (ctrl_num == 1 && slot == 0)
329 *addr = SPD_EEPROM_ADDRESS4;
330 else if (ctrl_num == 1 && slot == 1)
331 *addr = SPD_EEPROM_ADDRESS3;