2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 void fsl_ddr_board_options(memctl_options_t *popts,
16 unsigned int ctrl_num)
18 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
22 printf("Not supported controller number %d\n", ctrl_num);
29 * we use identical timing for all slots. If needed, change the code
30 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
32 if (popts->registered_dimm_en)
38 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
39 * freqency and n_banks specified in board_specific_parameters table.
41 ddr_freq = get_ddr_freq(0) / 1000000;
42 while (pbsp->datarate_mhz_high) {
43 if (pbsp->n_ranks == pdimm->n_ranks &&
44 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
45 if (ddr_freq <= pbsp->datarate_mhz_high) {
46 popts->clk_adjust = pbsp->clk_adjust;
47 popts->wrlvl_start = pbsp->wrlvl_start;
48 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
49 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
58 printf("Error: board specific timing not found for data rate %lu MT/s\n"
59 "Trying to use the highest speed (%u) parameters\n",
60 ddr_freq, pbsp_highest->datarate_mhz_high);
61 popts->clk_adjust = pbsp_highest->clk_adjust;
62 popts->wrlvl_start = pbsp_highest->wrlvl_start;
63 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
64 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
66 panic("DIMM is not supported by this board");
69 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
70 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
71 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
72 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
76 * Factors to consider for half-strength driver enable:
77 * - number of DIMMs installed
79 popts->half_strength_driver_enable = 1;
81 * Write leveling override
83 popts->wrlvl_override = 1;
84 popts->wrlvl_sample = 0xf;
87 * Rtt and Rtt_WR override
89 popts->rtt_override = 0;
91 /* Enable ZQ calibration */
94 #ifdef CONFIG_SYS_FSL_DDR4
95 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
96 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
97 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
99 /* DHC_EN =1, ODT = 75 Ohm */
100 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
101 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
105 #ifdef CONFIG_SYS_DDR_RAW_TIMING
106 dimm_params_t ddr_raw_timing = {
108 .rank_density = 1073741824u,
109 .capacity = 2147483648,
110 .primary_sdram_width = 64,
112 .registered_dimm = 0,
116 .n_banks_per_sdram_device = 8,
118 .burst_lengths_bitmask = 0x0c,
121 .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
132 .refresh_rate_ps = 7800000,
136 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
137 unsigned int controller_number,
138 unsigned int dimm_number)
140 const char dimm_model[] = "Fixed DDR on board";
142 if (((controller_number == 0) && (dimm_number == 0)) ||
143 ((controller_number == 1) && (dimm_number == 0))) {
144 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
145 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
146 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
152 phys_size_t initdram(int board_type)
154 phys_size_t dram_size;
156 puts("Initializing DDR....");
159 dram_size = fsl_ddr_sdram();
164 void dram_init_banksize(void)
166 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
167 if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
168 gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
169 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
170 gd->bd->bi_dram[1].size = gd->ram_size -
171 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
173 gd->bd->bi_dram[0].size = gd->ram_size;