1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 * Hayden Fraser (Hayden.Fraser@freescale.com)
11 #include <asm/immap.h>
14 DECLARE_GLOBAL_DATA_PTR;
19 puts("Freescale MCF5253 EVBE\n");
26 * Check to see if the SDRAM has already been initialized
27 * by a run control tool
29 if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
32 RC = (CONFIG_SYS_CLK / 1000000) >> 1;
35 /* Initialize DRAM Control Register: DCR */
36 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
39 mbar_writeLong(MCFSIM_DACR0, 0x00002320);
43 dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
44 mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
47 mbar_writeLong(MCFSIM_DACR0, 0x00002328);
50 /* Write to this block to initiate precharge */
51 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
54 /* Set RE bit in DACR */
55 mbar_writeLong(MCFSIM_DACR0,
56 mbar_readLong(MCFSIM_DACR0) | 0x8000);
59 /* Wait for at least 8 auto refresh cycles to occur */
62 /* Finish the configuration by issuing the MRS */
63 mbar_writeLong(MCFSIM_DACR0,
64 mbar_readLong(MCFSIM_DACR0) | 0x0040);
67 *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
70 gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
77 /* TODO: XXX XXX XXX */
78 printf("DRAM test not implemented!\n");
90 void ide_set_reset(int idereset)
92 atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
94 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
95 int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
96 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
97 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
98 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
99 {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
107 mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
109 #define CALC_TIMING(t) (t + period - 1) / period
110 period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
112 /*ata->ton = CALC_TIMING (180); */
113 out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
114 out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
115 out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
116 out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
117 out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
118 out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
119 out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
122 out_8(&ata->cr, 0x40);
125 setbits_8(&ata->cr, 0x01);
128 #endif /* CONFIG_IDE */