2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 int checkboard (void) {
12 puts ("Board: Freescale M5271EVB\n");
16 phys_size_t initdram (int board_type) {
20 /* Enable Address lines 23-21 and lower 16bits of data path */
21 mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
22 MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
25 /* Set CS2 pin to be SD_CS0 */
26 mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
27 | MCF_GPIO_PAR_CS_PAR_CS2);
29 /* Configure SDRAM Control Pin Assignemnt Register */
30 mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
31 MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
32 MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
33 MCF_GPIO_SDRAM_SDCS_11);
37 * Check to see if the SDRAM has already been initialized
38 * by a run control tool
40 if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
41 /* Initialize DRAM Control Register: DCR */
42 mbar_writeShort(MCF_SDRAMC_DCR,
43 MCF_SDRAMC_DCR_RTIM(2)
44 | MCF_SDRAMC_DCR_RC(0x2E));
51 * CBM: cmd at A20, bank select bits 21 and up
54 mbar_writeLong(MCF_SDRAMC_DACR0,
55 MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
56 | MCF_SDRAMC_DACRn_CASL(1)
57 | MCF_SDRAMC_DACRn_CBM(3)
58 | MCF_SDRAMC_DACRn_PS(0));
62 mbar_writeLong(MCF_SDRAMC_DMR0,
63 MCF_SDRAMC_DMRn_BAM_16M
67 /* Set IP bit in DACR */
68 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
69 | MCF_SDRAMC_DACRn_IP);
72 /* Wait at least 20ns to allow banks to precharge */
73 for (i = 0; i < 5; i++)
76 /* Write to this block to initiate precharge */
77 *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
80 /* Set RE bit in DACR */
81 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
82 | MCF_SDRAMC_DACRn_RE);
84 /* Wait for at least 8 auto refresh cycles to occur */
85 for (i = 0; i < 2000; i++)
88 /* Finish the configuration by issuing the MRS */
89 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
90 | MCF_SDRAMC_DACRn_MRS);
94 * Write to the SDRAM Mode Register A0-A11 = 0x400
96 * Write Burst Mode = Programmed Burst Length
97 * Op Mode = Standard Op
99 * Burst Type = Sequential
102 *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
106 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
109 int testdram (void) {
111 /* TODO: XXX XXX XXX */
112 printf ("DRAM test not implemented!\n");