2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/immap.h>
27 int checkboard (void) {
28 puts ("Board: Freescale M5271EVB\n");
32 phys_size_t initdram (int board_type) {
36 /* Enable Address lines 23-21 and lower 16bits of data path */
37 mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
38 MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
41 /* Set CS2 pin to be SD_CS0 */
42 mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
43 | MCF_GPIO_PAR_CS_PAR_CS2);
45 /* Configure SDRAM Control Pin Assignemnt Register */
46 mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
47 MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
48 MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
49 MCF_GPIO_SDRAM_SDCS_11);
53 * Check to see if the SDRAM has already been initialized
54 * by a run control tool
56 if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
57 /* Initialize DRAM Control Register: DCR */
58 mbar_writeShort(MCF_SDRAMC_DCR,
59 MCF_SDRAMC_DCR_RTIM(2)
60 | MCF_SDRAMC_DCR_RC(0x2E));
67 * CBM: cmd at A20, bank select bits 21 and up
70 mbar_writeLong(MCF_SDRAMC_DACR0,
71 MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
72 | MCF_SDRAMC_DACRn_CASL(1)
73 | MCF_SDRAMC_DACRn_CBM(3)
74 | MCF_SDRAMC_DACRn_PS(0));
78 mbar_writeLong(MCF_SDRAMC_DMR0,
79 MCF_SDRAMC_DMRn_BAM_16M
83 /* Set IP bit in DACR */
84 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
85 | MCF_SDRAMC_DACRn_IP);
88 /* Wait at least 20ns to allow banks to precharge */
89 for (i = 0; i < 5; i++)
92 /* Write to this block to initiate precharge */
93 *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
96 /* Set RE bit in DACR */
97 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
98 | MCF_SDRAMC_DACRn_RE);
100 /* Wait for at least 8 auto refresh cycles to occur */
101 for (i = 0; i < 2000; i++)
104 /* Finish the configuration by issuing the MRS */
105 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
106 | MCF_SDRAMC_DACRn_MRS);
110 * Write to the SDRAM Mode Register A0-A11 = 0x400
112 * Write Burst Mode = Programmed Burst Length
113 * Op Mode = Standard Op
115 * Burst Type = Sequential
118 *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
122 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
125 int testdram (void) {
127 /* TODO: XXX XXX XXX */
128 printf ("DRAM test not implemented!\n");