1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Board-specific sbf ddr/sdram init.
5 * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
14 /* Dram Initialization a1, a2, and d0 */
16 move.l #0xFC0A4074, %a1
17 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
20 /* SDRAM Chip 0 and 1 */
21 move.l #0xFC0B8110, %a1
22 move.l #0xFC0B8114, %a2
24 /* calculate the size */
26 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
27 #ifdef CONFIG_SYS_SDRAM_BASE1
36 #ifdef CONFIG_SYS_NAND_BOOT
37 beq asm_nand_chk_status
39 /* SDRAM Chip 0 and 1 */
40 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
42 #ifdef CONFIG_SYS_SDRAM_BASE1
43 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
48 /* dram cfg1 and cfg2 */
49 move.l #0xFC0B8008, %a1
50 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
52 move.l #0xFC0B800C, %a2
53 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
56 move.l #0xFC0B8000, %a1 /* Mode */
57 move.l #0xFC0B8004, %a2 /* Ctrl */
60 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
67 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
70 /* Perform two refresh cycles */
71 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
78 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
80 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
85 move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
86 and.l #0x7FFFFFFF, %d1