2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/immap.h>
32 typedef unsigned char FLASH_PORT_WIDTH;
33 typedef volatile unsigned char FLASH_PORT_WIDTHV;
35 #define FPW FLASH_PORT_WIDTH
36 #define FPWV FLASH_PORT_WIDTHV
38 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
39 #define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT
41 /* Intel-compatible flash commands */
42 #define INTEL_PROGRAM 0x00100010
43 #define INTEL_ERASE 0x00200020
44 #define INTEL_WRSETUP 0x00400040
45 #define INTEL_CLEAR 0x00500050
46 #define INTEL_LOCKBIT 0x00600060
47 #define INTEL_PROTECT 0x00010001
48 #define INTEL_STATUS 0x00700070
49 #define INTEL_READID 0x00900090
50 #define INTEL_CFIQRY 0x00980098
51 #define INTEL_SUSERASE 0x00B000B0
52 #define INTEL_PROTPROG 0x00C000C0
53 #define INTEL_CONFIRM 0x00D000D0
54 #define INTEL_WRBLK 0x00e800e8
55 #define INTEL_RESET 0x00FF00FF
57 /* Intel-compatible flash status bits */
58 #define INTEL_FINISHED 0x00800080
59 #define INTEL_OK 0x00800080
60 #define INTEL_ERASESUS 0x00600060
61 #define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS)
63 /* 28F160C3B CFI Data offset - This could vary */
64 #define INTEL_CFI_MFG 0x00 /* Manufacturer ID */
65 #define INTEL_CFI_PART 0x01 /* Product ID */
66 #define INTEL_CFI_LOCK 0x02 /* */
67 #define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */
68 #define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */
69 #define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */
70 #define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */
71 #define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */
72 #define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */
73 #define INTEL_CFI_CAP 0x28
74 #define INTEL_CFI_WRBUF 0x2A
75 #define INTEL_CFI_BANK 0x2C /* Number of Bank */
76 #define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */
77 #define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */
78 #define INTEL_CFI_SZ1A 0x2F /* Block Region Size */
79 #define INTEL_CFI_SZ1B 0x30
80 #define INTEL_CFI_BLK2A 0x31
81 #define INTEL_CFI_BLK2B 0x32
82 #define INTEL_CFI_SZ2A 0x33
83 #define INTEL_CFI_SZ2B 0x34
85 #define FLASH_CYCLE1 0x0555
86 #define FLASH_CYCLE2 0x0aaa
90 /* not in the flash.h yet */
91 #define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */
92 #define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */
93 #define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */
94 #define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */
95 #define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */
96 #define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */
98 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
99 #define STM_ID_M25P16 0x20152015
100 #define FLASH_M25P16 0x0055
103 #define SYNC __asm__("nop")
105 /*-----------------------------------------------------------------------
109 ulong flash_get_size(FPWV * addr, flash_info_t * info);
110 int flash_get_offsets(ulong base, flash_info_t * info);
111 int flash_cmd_rd(volatile u16 * addr, int index);
112 int write_data(flash_info_t * info, ulong dest, FPW data);
113 int write_data_block(flash_info_t * info, ulong src, ulong dest);
114 int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data);
115 void inline spin_wheel(void);
116 void flash_sync_real_protect(flash_info_t * info);
117 uchar intel_sector_protected(flash_info_t * info, ushort sector);
119 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
120 int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt);
121 int serial_flash_read_status(int chipsel);
122 static int ser_flash_cs = 0;
125 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
127 ulong flash_init(void)
133 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
137 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
138 memset(&flash_info[i], 0, sizeof(flash_info_t));
142 fbase = (ulong) CFG_FLASH0_BASE;
145 fbase = (ulong) CFG_FLASH1_BASE;
147 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
149 fbase = (ulong) CFG_FLASH2_BASE;
154 flash_get_size((FPWV *) fbase, &flash_info[i]);
155 flash_get_offsets((ulong) fbase, &flash_info[i]);
156 fbase += flash_info[i].size;
157 size += flash_info[i].size;
159 /* get the h/w and s/w protection status in sync */
160 flash_sync_real_protect(&flash_info[i]);
163 /* Protect monitor and environment sectors */
164 flash_protect(FLAG_PROTECT_SET,
166 CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
171 int flash_get_offsets(ulong base, flash_info_t * info)
174 int sectors, bs, banks;
176 if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
177 int sect[] = CFG_ATMEL_SECT;
178 int sectsz[] = CFG_ATMEL_SECTSZ;
180 info->start[0] = base;
181 for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) {
182 for (j = 0; j < sect[i]; j++, k++) {
183 info->start[k + 1] = info->start[k] + sectsz[i];
184 info->protect[k] = 0;
189 if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
190 volatile u16 *addr16 = (volatile u16 *)base;
192 *addr16 = (FPW) INTEL_RESET; /* restore read mode */
193 *addr16 = (FPW) INTEL_READID;
195 banks = addr16[INTEL_CFI_BANK] & 0xff;
198 info->start[0] = base;
200 for (k = 0, i = 0; i < banks; i++) {
201 /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
202 * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
203 * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
205 bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
206 | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
209 (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
211 for (j = 0; j < sectors; j++, k++) {
212 info->start[k + 1] = info->start[k] + bs;
216 *addr16 = (FPW) INTEL_RESET; /* restore read mode */
218 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
219 if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
220 info->start[0] = CFG_FLASH2_BASE;
221 for (k = 0, i = 0; i < CFG_STM_SECT; i++, k++) {
222 info->start[k + 1] = info->start[k] + CFG_STM_SECTSZ;
223 info->protect[k] = 0;
231 void flash_print_info(flash_info_t * info)
235 switch (info->flash_id & FLASH_VENDMASK) {
236 case FLASH_MAN_INTEL:
242 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
248 printf("Unknown Vendor ");
252 switch (info->flash_id & FLASH_TYPEMASK) {
254 printf("AT49BV040A\n");
256 case FLASH_28F128J3A:
257 printf("28F128J3A\n");
259 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
265 printf("Unknown Chip Type\n");
269 if (info->size > 0x100000) {
272 printf(" Size: %ld", info->size >> 20);
274 remainder = (info->size % 0x100000);
277 remainder = (int)((float)
278 (((float)remainder / (float)1024) *
280 printf(".%d ", remainder);
283 printf("MB in %d Sectors\n", info->sector_count);
285 printf(" Size: %ld KB in %d Sectors\n",
286 info->size >> 10, info->sector_count);
288 printf(" Sector Start Addresses:");
289 for (i = 0; i < info->sector_count; ++i) {
293 info->start[i], info->protect[i] ? " (RO)" : " ");
299 * The following code cannot be run from FLASH!
301 ulong flash_get_size(FPWV * addr, flash_info_t * info)
303 volatile u16 *addr16 = (volatile u16 *)addr;
304 int intel = 0, banks = 0;
308 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
309 if ((ulong) addr == CFG_FLASH2_BASE) {
315 dspi_tx(ser_flash_cs, 0x80, SER_RDID);
316 dspi_tx(ser_flash_cs, 0x80, 0);
317 dspi_tx(ser_flash_cs, 0x80, 0);
318 dspi_tx(ser_flash_cs, 0x80, 0);
321 manufactId = dspi_rx();
322 deviceId = dspi_rx() << 8;
323 deviceId |= dspi_rx();
325 dspi_tx(ser_flash_cs, 0x00, 0);
328 switch (manufactId) {
329 case (u8) STM_MANUFACT:
330 info->flash_id = FLASH_MAN_STM;
335 case (u16) STM_ID_M25P16:
336 info->flash_id += FLASH_M25P16;
340 info->sector_count = CFG_STM_SECT;
341 info->size = CFG_STM_SECT * CFG_STM_SECTSZ;
347 addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
348 addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
349 addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
351 switch (addr[0] & 0xff) {
352 case (u8) ATM_MANUFACT:
353 info->flash_id = FLASH_MAN_ATM;
356 case (u8) INTEL_MANUFACT:
357 /* Terminate Atmel ID read */
358 addr[0] = (FPWV) 0x00F000F0;
359 /* Write auto select command: read Manufacturer ID */
360 /* Write auto select command sequence and test FLASH answer */
361 *addr16 = (FPW) INTEL_RESET; /* restore read mode */
362 *addr16 = (FPW) INTEL_READID;
364 info->flash_id = FLASH_MAN_INTEL;
365 value = (addr16[INTEL_CFI_MFG] << 8);
366 value |= addr16[INTEL_CFI_PART] & 0xff;
370 printf("Unknown Flash\n");
371 info->flash_id = FLASH_UNKNOWN;
372 info->sector_count = 0;
375 *addr = (FPW) 0x00F000F0;
376 *addr = (FPW) INTEL_RESET; /* restore read mode */
377 return (0); /* no or unknown flash */
381 case (u8) ATM_ID_LV040:
382 info->flash_id += FLASH_AT040;
384 case (u16) INTEL_ID_28F128J3:
385 info->flash_id += FLASH_28F128J3A;
387 case (u16) INTEL_ID_28F64P30T:
388 info->flash_id += FLASH_28F64P30T;
390 case (u16) INTEL_ID_28F64P30B:
391 info->flash_id += FLASH_28F64P30B;
393 case (u16) INTEL_ID_28F128P30T:
394 info->flash_id += FLASH_28F128P30T;
396 case (u16) INTEL_ID_28F128P30B:
397 info->flash_id += FLASH_28F128P30B;
399 case (u16) INTEL_ID_28F256P30T:
400 info->flash_id += FLASH_28F256P30T;
402 case (u16) INTEL_ID_28F256P30B:
403 info->flash_id += FLASH_28F256P30B;
406 info->flash_id = FLASH_UNKNOWN;
411 /* Intel spec. under CFI section */
415 banks = addr16[INTEL_CFI_BANK] & 0xff;
418 for (i = 0; i < banks; i++) {
419 /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
420 * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
421 * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
423 bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
424 | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
427 (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
428 sz += (bs * sectors);
431 info->sector_count = sectors;
433 *addr = (FPW) INTEL_RESET; /* restore read mode */
435 int sect[] = CFG_ATMEL_SECT;
436 int sectsz[] = CFG_ATMEL_SECTSZ;
438 info->sector_count = 0;
440 for (i = 0; i < CFG_ATMEL_REGION; i++) {
441 info->sector_count += sect[i];
442 info->size += sect[i] * sectsz[i];
446 addr[0] = (FPWV) 0x00F000F0;
449 if (info->sector_count > CFG_MAX_FLASH_SECT) {
450 printf("** ERROR: sector count %d > max (%d) **\n",
451 info->sector_count, CFG_MAX_FLASH_SECT);
452 info->sector_count = CFG_MAX_FLASH_SECT;
458 int flash_cmd_rd(volatile u16 * addr, int index)
460 return (int)addr[index];
463 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
464 int serial_flash_read_status(int chipsel)
468 dspi_tx(chipsel, 0x80, SER_RDSR);
471 dspi_tx(chipsel, 0x00, 0);
479 * This function gets the u-boot flash sector protection status
480 * (flash_info_t.protect[]) in sync with the sector protection
481 * status stored in hardware.
483 void flash_sync_real_protect(flash_info_t * info)
487 switch (info->flash_id & FLASH_TYPEMASK) {
488 case FLASH_28F160C3B:
489 case FLASH_28F160C3T:
490 case FLASH_28F320C3B:
491 case FLASH_28F320C3T:
492 case FLASH_28F640C3B:
493 case FLASH_28F640C3T:
494 for (i = 0; i < info->sector_count; ++i) {
495 info->protect[i] = intel_sector_protected(info, i);
499 /* no h/w protect support */
505 * checks if "sector" in bank "info" is protected. Should work on intel
506 * strata flash chips 28FxxxJ3x in 8-bit mode.
507 * Returns 1 if sector is protected (or timed-out while trying to read
508 * protection status), 0 if it is not.
510 uchar intel_sector_protected(flash_info_t * info, ushort sector)
513 FPWV *lock_conf_addr;
518 * first, wait for the WSM to be finished. The rationale for
519 * waiting for the WSM to become idle for at most
520 * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
521 * because of: (1) erase, (2) program or (3) lock bit
522 * configuration. So we just wait for the longest timeout of
523 * the (1)-(3), i.e. the erase timeout.
526 /* wait at least 35ns (W12) before issuing Read Status Register */
528 addr = (FPWV *) info->start[sector];
529 *addr = (FPW) INTEL_STATUS;
531 start = get_timer(0);
532 while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
533 if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
534 *addr = (FPW) INTEL_RESET; /* restore read mode */
535 printf("WSM busy too long, can't get prot status\n");
540 /* issue the Read Identifier Codes command */
541 *addr = (FPW) INTEL_READID;
543 /* Intel example code uses offset of 4 for 8-bit flash */
544 lock_conf_addr = (FPWV *) info->start[sector];
545 ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0;
547 /* put flash back in read mode */
548 *addr = (FPW) INTEL_RESET;
553 int flash_erase(flash_info_t * info, int s_first, int s_last)
555 int flag, prot, sect;
556 ulong type, start, last;
557 int rcode = 0, flashtype = 0;
558 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
562 if ((s_first < 0) || (s_first > s_last)) {
563 if (info->flash_id == FLASH_UNKNOWN)
564 printf("- missing\n");
566 printf("- no sectors to erase\n");
570 type = (info->flash_id & FLASH_VENDMASK);
576 case FLASH_MAN_INTEL:
579 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
585 type = (info->flash_id & FLASH_VENDMASK);
586 printf("Can't erase unknown flash type %08lx - aborted\n",
592 for (sect = s_first; sect <= s_last; ++sect) {
593 if (info->protect[sect]) {
599 printf("- Warning: %d protected sectors will not be erased!\n",
604 start = get_timer(0);
607 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
608 /* Perform bulk erase */
609 if (flashtype == 3) {
610 if ((s_last - s_first) == (CFG_STM_SECT - 1)) {
612 dspi_tx(ser_flash_cs, 0x00, SER_WREN);
615 status = serial_flash_read_status(ser_flash_cs);
616 if (((status & 0x9C) != 0)
617 && ((status & 0x02) != 0x02)) {
618 printf("Can't erase flash\n");
622 dspi_tx(ser_flash_cs, 0x00, SER_BULK_ERASE);
626 start = get_timer(0);
629 serial_flash_read_status
632 if (count++ > 0x10000) {
637 if (get_timer(start) >
638 CFG_FLASH_ERASE_TOUT) {
642 } while (status & 0x01);
644 printf("\b. done\n");
646 } else if (prot == CFG_STM_SECT) {
652 /* Start erase on unprotected sectors */
653 for (sect = s_first; sect <= s_last; sect++) {
654 if (info->protect[sect] == 0) { /* not protected */
656 FPWV *addr = (FPWV *) (info->start[sect]);
661 /* arm simple, non interrupt dependent timer */
662 start = get_timer(0);
667 FPWV *base; /* first address in bank */
670 flag = disable_interrupts();
672 atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
673 base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
675 base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
676 base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
677 base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
678 base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
679 base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
680 *atmeladdr = (u8) 0x00300030; /* erase sector */
685 while ((*atmeladdr & (u8) 0x00800080) !=
687 if (get_timer(start) >
688 CFG_FLASH_ERASE_TOUT) {
690 *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
697 *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
703 *addr = (FPW) INTEL_READID;
704 min = addr[INTEL_CFI_TERB] & 0xff;
705 min = 1 << min; /* ms */
706 min = (min / info->sector_count) * 1000;
708 /* start erase block */
709 *addr = (FPW) INTEL_CLEAR; /* clear status register */
710 *addr = (FPW) INTEL_ERASE; /* erase setup */
711 *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
713 while ((*addr & (FPW) INTEL_FINISHED) !=
714 (FPW) INTEL_FINISHED) {
716 if (get_timer(start) >
717 CFG_FLASH_ERASE_TOUT) {
719 *addr = (FPW) INTEL_SUSERASE; /* suspend erase */
720 *addr = (FPW) INTEL_RESET; /* reset to read mode */
727 *addr = (FPW) INTEL_RESET; /* resest to read mode */
731 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
734 u8 sec = ((ulong) addr >> 16) & 0xFF;
736 dspi_tx(ser_flash_cs, 0x00, SER_WREN);
739 serial_flash_read_status
741 if (((status & 0x9C) != 0)
742 && ((status & 0x02) != 0x02)) {
743 printf("Error Programming\n");
747 dspi_tx(ser_flash_cs, 0x80,
749 dspi_tx(ser_flash_cs, 0x80, sec);
750 dspi_tx(ser_flash_cs, 0x80, 0);
751 dspi_tx(ser_flash_cs, 0x00, 0);
760 serial_flash_read_status
763 if (get_timer(start) >
764 CFG_FLASH_ERASE_TOUT) {
768 } while (status & 0x01);
773 } /* switch (flashtype) */
781 int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
785 if (info->flash_id == FLASH_UNKNOWN)
788 switch (info->flash_id & FLASH_VENDMASK) {
792 int bytes; /* number of bytes to program in current word */
793 int left; /* number of bytes left to program */
796 for (left = cnt, res = 0;
797 left > 0 && res == 0;
798 addr += sizeof(data), left -=
799 sizeof(data) - bytes) {
801 bytes = addr & (sizeof(data) - 1);
802 addr &= ~(sizeof(data) - 1);
804 /* combine source and destination data so can program
805 * an entire word of 16 or 32 bits
807 for (i = 0; i < sizeof(data); i++) {
809 if (i < bytes || i - bytes >= left)
810 data += *((uchar *) addr + i);
815 data = (data >> 8) | (data << 8);
816 res = write_word_atm(info, (FPWV *) addr, data);
819 } /* case FLASH_MAN_ATM */
821 case FLASH_MAN_INTEL:
825 int i, l, rc, port_width;
827 /* get lower word aligned address */
829 port_width = sizeof(FPW);
832 * handle unaligned start bytes
834 if ((l = addr - wp) != 0) {
836 for (i = 0, cp = wp; i < l; ++i, ++cp) {
837 data = (data << 8) | (*(uchar *) cp);
840 for (; i < port_width && cnt > 0; ++i) {
841 data = (data << 8) | *src++;
846 for (; cnt == 0 && i < port_width; ++i, ++cp)
847 data = (data << 8) | (*(uchar *) cp);
849 if ((rc = write_data(info, wp, data)) != 0)
855 if (cnt > WR_BLOCK) {
857 * handle word aligned part
860 while (cnt >= WR_BLOCK) {
863 write_data_block(info,
872 if (count++ > 0x800) {
879 /* handle word aligned part */
880 if (cnt < WR_BLOCK) {
882 * handle word aligned part
885 while (cnt >= port_width) {
887 for (i = 0; i < port_width; ++i)
888 data = (data << 8) | *src++;
892 (ulong) ((FPWV *) wp),
898 if (count++ > 0x800) {
909 * handle unaligned tail bytes
912 for (i = 0, cp = wp; i < port_width && cnt > 0;
914 data = (data << 8) | (*src++);
917 for (; i < port_width; ++i, ++cp) {
918 data = (data << 8) | (*(uchar *) cp);
921 return write_data(info, (ulong) ((FPWV *) wp),
924 } /* case FLASH_MAN_INTEL */
926 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
930 u8 *data = (u8 *) src;
931 int left; /* number of bytes left to program */
935 /* page align, each page is 256 bytes */
936 if ((wp % 0x100) != 0) {
937 left = (0x100 - (wp & 0xFF));
938 write_ser_data(info, wp, data, left);
944 /* page program - 256 bytes at a time */
947 while (cnt >= 0x100) {
948 write_ser_data(info, wp, data, 0x100);
953 if (count++ > 0x400) {
960 /* remainint bytes */
961 if (cnt && (cnt < 256)) {
962 write_ser_data(info, wp, data, cnt);
976 /*-----------------------------------------------------------------------
977 * Write a word or halfword to Flash, returns:
980 * 2 - Flash not erased
982 int write_data_block(flash_info_t * info, ulong src, ulong dest)
984 FPWV *srcaddr = (FPWV *) src;
985 FPWV *dstaddr = (FPWV *) dest;
989 /* Check if Flash is (sufficiently) erased */
990 for (i = 0; i < WR_BLOCK; i++)
991 if ((*dstaddr++ & 0xff) != 0xff) {
992 printf("not erased at %08lx (%lx)\n",
993 (ulong) dstaddr, *dstaddr);
997 dstaddr = (FPWV *) dest;
999 /* Disable interrupts which might cause a timeout here */
1000 flag = disable_interrupts();
1002 *dstaddr = (FPW) INTEL_WRBLK; /* write block setup */
1005 enable_interrupts();
1007 /* arm simple, non interrupt dependent timer */
1008 start = get_timer(0);
1010 /* wait while polling the status register */
1011 while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
1012 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
1013 *dstaddr = (FPW) INTEL_RESET; /* restore read mode */
1018 *dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */
1019 for (i = 0; i < WR_BLOCK; i++)
1020 *dstaddr++ = *srcaddr++;
1023 *dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */
1025 /* arm simple, non interrupt dependent timer */
1026 start = get_timer(0);
1028 /* wait while polling the status register */
1029 while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
1030 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
1031 *dstaddr = (FPW) INTEL_RESET; /* restore read mode */
1036 *dstaddr = (FPW) INTEL_RESET; /* restore read mode */
1041 /*-----------------------------------------------------------------------
1042 * Write a word or halfword to Flash, returns:
1045 * 2 - Flash not erased
1047 int write_data(flash_info_t * info, ulong dest, FPW data)
1049 FPWV *addr = (FPWV *) dest;
1053 /* Check if Flash is (sufficiently) erased */
1054 if ((*addr & data) != data) {
1055 printf("not erased at %08lx (%lx)\n", (ulong) addr,
1060 /* Disable interrupts which might cause a timeout here */
1061 flag = (int)disable_interrupts();
1063 *addr = (FPW) INTEL_CLEAR;
1064 *addr = (FPW) INTEL_RESET;
1066 *addr = (FPW) INTEL_WRSETUP; /* write setup */
1070 enable_interrupts();
1072 /* arm simple, non interrupt dependent timer */
1073 start = get_timer(0);
1075 /* wait while polling the status register */
1076 while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) {
1077 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
1078 *addr = (FPW) INTEL_SUSERASE; /* suspend mode */
1079 *addr = (FPW) INTEL_CLEAR; /* clear status */
1080 *addr = (FPW) INTEL_RESET; /* reset */
1085 *addr = (FPW) INTEL_CLEAR; /* clear status */
1086 *addr = (FPW) INTEL_RESET; /* restore read mode */
1091 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
1092 int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt)
1098 /* Check if Flash is (sufficiently) erased */
1099 dspi_tx(ser_flash_cs, 0x80, SER_READ);
1100 dspi_tx(ser_flash_cs, 0x80, (dest >> 16) & 0xFF);
1101 dspi_tx(ser_flash_cs, 0x80, (dest >> 8) & 0xFF);
1102 dspi_tx(ser_flash_cs, 0x80, dest & 0xFF);
1107 dspi_tx(ser_flash_cs, 0x80, 0);
1108 flashdata = dspi_rx();
1109 dspi_tx(ser_flash_cs, 0x00, 0);
1112 if ((flashdata & *data) != *data) {
1113 printf("not erased at %08lx (%lx)\n", (ulong) dest,
1118 dspi_tx(ser_flash_cs, 0x00, SER_WREN);
1121 status = serial_flash_read_status(ser_flash_cs);
1122 if (((status & 0x9C) != 0) && ((status & 0x02) != 0x02)) {
1123 printf("Error Programming\n");
1127 start = get_timer(0);
1129 dspi_tx(ser_flash_cs, 0x80, SER_PAGE_PROG);
1130 dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF0000) >> 16));
1131 dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF00) >> 8));
1132 dspi_tx(ser_flash_cs, 0x80, (dest & 0xFF));
1138 for (i = 0; i < (cnt - 1); i++) {
1139 dspi_tx(ser_flash_cs, 0x80, *data);
1144 dspi_tx(ser_flash_cs, 0x00, *data);
1148 status = serial_flash_read_status(ser_flash_cs);
1150 if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
1151 printf("Timeout\n");
1154 } while (status & 0x01);
1160 /*-----------------------------------------------------------------------
1161 * Write a word to Flash for ATMEL FLASH
1162 * A word is 16 bits, whichever the bus width of the flash bank
1163 * (not an individual chip) is.
1168 * 2 - Flash not erased
1170 int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data)
1174 int res = 0; /* result, assume success */
1175 FPWV *base; /* first address in flash bank */
1177 /* Check if Flash is (sufficiently) erased */
1178 if ((*((volatile u16 *)dest) & data) != data) {
1182 base = (FPWV *) (CFG_ATMEL_BASE);
1184 for (i = 0; i < sizeof(u16); i++) {
1185 /* Disable interrupts which might cause a timeout here */
1186 flag = disable_interrupts();
1188 base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
1189 base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
1190 base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */
1192 *dest = data; /* start programming the data */
1194 /* re-enable interrupts if necessary */
1196 enable_interrupts();
1198 start = get_timer(0);
1200 /* data polling for D7 */
1202 && (*dest & (u8) 0x00800080) !=
1203 (data & (u8) 0x00800080)) {
1204 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
1205 *dest = (u8) 0x00F000F0; /* reset bank */
1210 *dest++ = (u8) 0x00F000F0; /* reset bank */
1217 void inline spin_wheel(void)
1220 static char w[] = "\\/-";
1222 printf("\010%c", w[p]);
1223 (++p == 3) ? (p = 0) : 0;
1226 #ifdef CFG_FLASH_PROTECTION
1227 /*-----------------------------------------------------------------------
1229 int flash_real_protect(flash_info_t * info, long sector, int prot)
1231 int rcode = 0; /* assume success */
1232 FPWV *addr; /* address of sector */
1235 addr = (FPWV *) (info->start[sector]);
1237 switch (info->flash_id & FLASH_TYPEMASK) {
1238 case FLASH_28F160C3B:
1239 case FLASH_28F160C3T:
1240 case FLASH_28F320C3B:
1241 case FLASH_28F320C3T:
1242 case FLASH_28F640C3B:
1243 case FLASH_28F640C3T:
1244 *addr = (FPW) INTEL_RESET; /* make sure in read mode */
1245 *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */
1248 *addr = (FPW) INTEL_PROTECT; /* lock sector */
1250 *addr = (FPW) INTEL_CONFIRM; /* unlock sector */
1252 /* now see if it really is locked/unlocked as requested */
1253 *addr = (FPW) INTEL_READID;
1255 /* read sector protection at sector address, (A7 .. A0) = 0x02.
1256 * D0 = 1 for each device if protected.
1257 * If at least one device is protected the sector is marked
1258 * protected, but return failure. Mixed protected and
1259 * unprotected devices within a sector should never happen.
1261 value = addr[2] & (FPW) INTEL_PROTECT;
1263 info->protect[sector] = 0;
1264 else if (value == (FPW) INTEL_PROTECT)
1265 info->protect[sector] = 1;
1267 /* error, mixed protected and unprotected */
1269 info->protect[sector] = 1;
1271 if (info->protect[sector] != prot)
1272 rcode = 1; /* failed to protect/unprotect as requested */
1274 /* reload all protection bits from hardware for now */
1275 flash_sync_real_protect(info);
1279 /* no hardware protect that we support */
1280 info->protect[sector] = prot;