2 * Board-specific sbf ddr/sdram init.
4 * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
6 * SPDX-License-Identifier: GPL-2.0+
15 /* Dram Initialization a1, a2, and d0 */
17 move.l #0xFC0A4074, %a1
18 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
21 /* SDRAM Chip 0 and 1 */
22 move.l #0xFC0B8110, %a1
23 move.l #0xFC0B8114, %a2
25 /* calculate the size */
27 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
28 #ifdef CONFIG_SYS_SDRAM_BASE1
37 #ifdef CONFIG_SYS_NAND_BOOT
38 beq asm_nand_chk_status
40 /* SDRAM Chip 0 and 1 */
41 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
43 #ifdef CONFIG_SYS_SDRAM_BASE1
44 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
49 /* dram cfg1 and cfg2 */
50 move.l #0xFC0B8008, %a1
51 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
53 move.l #0xFC0B800C, %a2
54 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
57 move.l #0xFC0B8000, %a1 /* Mode */
58 move.l #0xFC0B8004, %a2 /* Ctrl */
61 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
65 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
67 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
74 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
77 /* Perform two refresh cycles */
78 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
84 move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
90 move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
91 and.l #0x7FFFFFFF, %d1