2 * (C) Copyright 2007 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/bitops.h>
28 #include <asm/processor.h>
29 #include <fdt_support.h>
30 #ifdef CONFIG_MISC_INIT_R
34 DECLARE_GLOBAL_DATA_PTR;
36 extern int mpc5121_diu_init(void);
39 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
40 CLOCK_SCCR1_LPC_EN | \
41 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
42 CLOCK_SCCR1_PSCFIFO_EN | \
43 CLOCK_SCCR1_DDR_EN | \
44 CLOCK_SCCR1_FEC_EN | \
45 CLOCK_SCCR1_PATA_EN | \
46 CLOCK_SCCR1_PCI_EN | \
49 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
50 CLOCK_SCCR2_SPDIF_EN | \
51 CLOCK_SCCR2_DIU_EN | \
54 #define CSAW_START(start) ((start) & 0xFFFF0000)
55 #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
57 long int fixed_sdram(void);
59 int board_early_init_f (void)
61 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
65 * Initialize Local Window for the CPLD registers access (CS2 selects
68 im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) |
69 CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE);
70 im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG;
73 * According to MPC5121e RM, configuring local access windows should
74 * be followed by a dummy read of the config register that was
75 * modified last and an isync
77 lpcaw = im->sysconf.lpcs2aw;
78 __asm__ __volatile__ ("isync");
81 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
83 * Without this the flash identification routine fails, as it needs to issue
84 * write commands in order to establish the device ID.
87 #ifdef CONFIG_ADS5121_REV2
88 *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
90 if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
91 *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
93 /* running from Backup flash */
94 *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32;
98 * Configure Flash Speed
100 *((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG;
101 if (SVR_MJREV (im->sysconf.spridr) >= 2) {
102 *((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING;
107 im->clk.sccr[0] = SCCR1_CLOCKS_EN;
108 im->clk.sccr[1] = SCCR2_CLOCKS_EN;
109 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
110 im->clk.sccr[1] |= CLOCK_SCCR2_IIM_EN;
116 phys_size_t initdram (int board_type)
120 msize = fixed_sdram ();
126 * fixed sdram init -- the board doesn't use memory modules that have serial presence
127 * detect or similar mechanism for discovery of the DRAM settings
129 long int fixed_sdram (void)
131 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
132 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
133 u32 msize_log2 = __ilog2 (msize);
136 /* Initialize IO Control */
137 im->io_ctrl.io_control_mem = IOCTRL_MUX_DDR;
139 /* Initialize DDR Local Window */
140 im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
141 im->sysconf.ddrlaw.ar = msize_log2 - 1;
144 * According to MPC5121e RM, configuring local access windows should
145 * be followed by a dummy read of the config register that was
146 * modified last and an isync
148 i = im->sysconf.ddrlaw.ar;
149 __asm__ __volatile__ ("isync");
152 im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
154 /* Initialize DDR Priority Manager */
155 im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
156 im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
157 im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
158 im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
159 im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
160 im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
161 im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
162 im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
163 im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
164 im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
165 im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
166 im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
167 im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
168 im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
169 im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
170 im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
171 im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
172 im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
173 im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
174 im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
175 im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
176 im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
177 im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
179 /* Initialize MDDRC */
180 im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
181 im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
182 im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
183 im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
186 for (i = 0; i < 10; i++)
187 im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
189 im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
190 im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
191 im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
192 im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
193 im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
194 im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
195 im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
196 im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
197 im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
198 im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
199 im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
200 im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
201 im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
202 im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
203 im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
204 im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
205 im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
206 im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
207 im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
208 im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
209 im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
212 im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
213 im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
218 int misc_init_r(void)
222 /* Using this for DIU init before the driver in linux takes over
223 * Enable the TFP410 Encoder (I2C address 0x38)
228 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
229 /* Verify if enabled */
231 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
232 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
235 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
236 /* Verify if enabled */
238 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
239 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
241 #ifdef CONFIG_FSL_DIU_FB
242 # if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
249 static iopin_t ioregs_init[] = {
250 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
252 IOCTL_SPDIF_TXCLK, 3, 0,
253 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
254 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
256 /* Set highest Slew on 9 PATA pins */
258 IOCTL_PATA_CE1, 9, 1,
259 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
260 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
262 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
265 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
266 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
268 /* FUNC1=SPDIF_TXCLK */
271 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
272 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
274 /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
276 IOCTL_I2C1_SCL, 2, 0,
277 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
278 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
283 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
284 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
286 /* FUNC2=DIU_HSYNC */
289 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
290 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
292 /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
295 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
296 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
300 static iopin_t rev2_silicon_pci_ioregs_init[] = {
301 /* FUNC0=PCI Sets next 54 to PCI pads */
303 IOCTL_PCI_AD31, 54, 0,
304 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
308 int checkboard (void)
310 ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
311 uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
312 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
314 printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
317 /* initialize function mux & slew rate IO inter alia on IO Pins */
318 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
320 if (SVR_MJREV (im->sysconf.spridr) >= 2)
321 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
326 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
327 void ft_board_setup(void *blob, bd_t *bd)
329 ft_cpu_setup(blob, bd);
330 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
332 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */