2 * (C) Copyright 2004-05; Tundra Semiconductor Corp.
4 * Added automatic detect of SDC settings
5 * Copyright (c) 2005 Freescale Semiconductor, Inc.
6 * Maintainer tie-fei.zang@freescale.com
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * FILENAME: asm_init.s
27 * Originator: Alex Bounine
30 * Initialization code for the Tundra Tsi108 bridge chip
37 #include <ppc_asm.tmpl>
39 #include <asm/processor.h>
44 * Build Configuration Options
47 /* #define DISABLE_PBM disables usage of PB Master */
48 /* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */
49 /* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */
52 * Hardcoded SDC settings
55 #ifdef SDC_HARDCODED_INIT
57 /* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */
59 #define VAL_SD_REFRESH (0x61A)
60 #define VAL_SD_TIMING (0x0308336b)
61 #define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */
62 #define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */
63 #define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */
64 #define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */
66 #endif /* SDC_HARDCODED_INIT */
71 CPU Address and Data Parity enables.
79 * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
80 * expected to work correctly for the CSR space within 32KB range.
82 * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
83 * These macros are absolutely identical except their names. This difference
84 * is provided intentionally for better readable code.
87 #define LOAD_PTR(reg,const32) \
88 addis reg,r0,const32@h; ori reg,reg,const32@l
90 #define LOAD_U32(reg,const32) \
91 addis reg,r0,const32@h; ori reg,reg,const32@l
93 /* LOADMEM initializes a register with the contents of a specified 32-bit
94 * memory location, usually a CSR value.
97 #define LOAD_MEM(reg,addr32) \
98 addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
100 #ifndef SDC_HARDCODED_INIT
102 /* MHz: 0,0,183,100,133,167,200,233 */
103 .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */
107 * board_asm_init() - early initialization function. Coded to be portable to
108 * dual-CPU configuration.
109 * Checks CPU number and performs board HW initialization if called for CPU0.
110 * Registers used: r3,r4,r5,r6,r19,r29
112 * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
113 * and the rest of the board. Current implementation demonstrates two
114 * possible ways to identify CPU number:
115 * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
116 * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
119 .globl board_asm_init
121 mflr r19 /* Save LR to be able return later. */
122 bl icache_enable /* Enable icache to reduce reads from flash. */
124 /* Initialize pointer to Tsi108 register space */
126 LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
127 ori r4,r29,TSI108_PB_REG_OFFSET
129 /* Check Processor Version Number */
132 rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */
134 cmpli 0,0,r3,0x8000 /* MPC74xx */
138 * For MPC744x/5x enable extended BATs[4-7]
139 * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
140 * to disable prefetch
144 oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */
145 ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */
150 /* Adding code to disable external interventions in MPX bus mode */
152 oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */
157 /* Sri: code to enable FP unit */
164 /* def CONFIG_DUAL_CPU
165 * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
168 mfspr r3,1014 /* read MSSCR0 */
169 rlwinm. r3,r3,27,31,31 /* get processor ID number */
170 mtspr SPRN_PIR,r3 /* Save CPU ID */
177 /* An alternative method of checking the processor number (in addition
178 * to configuration using MSSCR0[ID] bit on MPC74xx).
179 * Good for IBM PPC750FX/GX.
182 lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */
183 rlwinm. r3,r3,24,31,31 /* get processor ID number */
189 #endif /* CONFIG_DUAL_CPU */
191 /* Initialize Tsi108 chip */
196 * Adjust HLP/Flash parameters. By default after reset the HLP port is
197 * set to support slow devices. Better performance can be achived when
198 * an optimal parameters are used for specific EPROM device.
199 * NOTE: This should be performed ASAP for the emulation platform
200 * because it has 5MHz HLP clocking.
203 #ifdef CONFIG_TSI108EMU
204 ori r4,r29,TSI108_HLP_REG_OFFSET
205 LOAD_U32(r5,0x434422c0)
206 stw r5,0x08(r4) /* set HLP B0_CTRL0 */
208 LOAD_U32(r5,0xd0012000)
209 stw r5,0x0c(r4) /* set HLP B0_CTRL1 */
213 /* Initialize PB interface. */
215 ori r4,r29,TSI108_PB_REG_OFFSET
217 #if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE)
218 /* Relocate (if required) Tsi108 registers. Set new value for
220 * Note we are in the 32-bit address mode.
222 LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
223 stw r5,PB_REG_BAR(r4)
226 ori r4,r29,TSI108_PB_REG_OFFSET
229 /* Set PB Slave configuration register */
231 LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */
232 lwz r3, PB_RSR(r4) /* get PB bus mode */
233 xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
234 rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */
238 /* Configure PB Arbiter */
240 lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
241 li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */
243 ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */
245 andc r5,r5,r3 /* Clear the masked bit fields */
246 ori r5,r5,0x0001 /* Set pipeline depth */
247 stw r5,PB_ARB_CTRL(r4)
249 #if (0) /* currently using the default settings for PBM after reset */
250 LOAD_U32(r5,0x) /* value for PB_MCR */
254 LOAD_U32(r5,0x) /* value for PB_MCMD */
259 /* Disable or enable PVT based on processor bus frequency
260 * 1. Read CG_PWRUP_STATUS register field bits 18,17,16
261 * 2. See if the value is < or > 133mhz (18:16 = 100)
265 LOAD_U32(r3,0xC0002234)
267 rlwinm r3,r3,16,29,31
272 #ifndef CONFIG_TSI108EMU
273 /* FIXME: Disable PB calibration control for any real Tsi108 board */
274 li r5,0x0101 /* disable calibration control */
275 stw r5,PB_PVT_CTRL2(r4)
279 /* Initialize SDRAM controller. */
283 #ifndef SDC_HARDCODED_INIT
284 /* get SDC clock prior doing sdram controller autoconfig */
285 ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */
286 lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */
287 rlwinm r3,r3,12,29,31 /* r3 - SD clk */
288 lis r5,sdc_clk_sync@h
289 ori r5,r5,sdc_clk_sync@l
290 /* Sri: At this point check if r3 = 001. If yes,
291 * the memory frequency should be same as the
296 lwz r6, CG_PWRUP_STATUS(r4)
297 rlwinm r6,r6,16,29,31
302 lwzx r9,r5,r3 /* get SD clk rate in nSec */
303 /* ATTN: r9 will be used by SPD routine */
304 #endif /* !SDC_HARDCODED_INIT */
306 ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */
308 /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */
311 stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */
312 #ifdef ENABLE_SDRAM_ECC
314 #endif /* ENABLE_SDRAM_ECC */
315 stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */
318 #ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
320 /* First read the CG_PWRUP_STATUS register to get the
321 * memory speed from bits 22,21,20
324 LOAD_U32(r3,0xC0002234)
326 rlwinm r3,r3,12,29,31
328 /* Now first check for 166, then 200, or default */
333 /* set values for 166 Mhz memory speed
334 * Set refresh rate and timing parameters
336 LOAD_U32(r5,0x00000515)
337 stw r5,SD_REFRESH(r4)
338 LOAD_U32(r5,0x03073368)
342 /* Initialize DIMM0 control and BAR registers */
343 LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
344 #ifdef SDC_AUTOPRECH_EN
345 oris r5,r5,0x0001 /* set auto precharge EN bit */
347 stw r5,SD_D0_CTRL(r4)
348 LOAD_U32(r5,VAL_SD_D0_BAR)
352 /* Initialize DIMM1 control and BAR registers
353 * (same as dimm 0, next 512MB, disabled)
355 LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
356 #ifdef SDC_AUTOPRECH_EN
357 oris r5,r5,0x0001 /* set auto precharge EN bit */
359 stw r5,SD_D1_CTRL(r4)
360 LOAD_U32(r5,VAL_SD_D1_BAR)
369 bne set_default_values
371 /* set values for 200Mhz memory speed
372 * Set refresh rate and timing parameters
374 LOAD_U32(r5,0x0000061a)
375 stw r5,SD_REFRESH(r4)
376 LOAD_U32(r5,0x03083348)
380 /* Initialize DIMM0 control and BAR registers */
381 LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
382 #ifdef SDC_AUTOPRECH_EN
383 oris r5,r5,0x0001 /* set auto precharge EN bit */
385 stw r5,SD_D0_CTRL(r4)
386 LOAD_U32(r5,VAL_SD_D0_BAR)
390 /* Initialize DIMM1 control and BAR registers
391 * (same as dimm 0, next 512MB, disabled)
393 LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
394 #ifdef SDC_AUTOPRECH_EN
395 oris r5,r5,0x0001 /* set auto precharge EN bit */
397 stw r5,SD_D1_CTRL(r4)
398 LOAD_U32(r5,VAL_SD_D1_BAR)
406 /* Set refresh rate and timing parameters */
407 LOAD_U32(r5,VAL_SD_REFRESH)
408 stw r5,SD_REFRESH(r4)
409 LOAD_U32(r5,VAL_SD_TIMING)
413 /* Initialize DIMM0 control and BAR registers */
414 LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
415 #ifdef SDC_AUTOPRECH_EN
416 oris r5,r5,0x0001 /* set auto precharge EN bit */
418 stw r5,SD_D0_CTRL(r4)
419 LOAD_U32(r5,VAL_SD_D0_BAR)
423 /* Initialize DIMM1 control and BAR registers
424 * (same as dimm 0, next 512MB, disabled)
426 LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
427 #ifdef SDC_AUTOPRECH_EN
428 oris r5,r5,0x0001 /* set auto precharge EN bit */
430 stw r5,SD_D1_CTRL(r4)
431 LOAD_U32(r5,VAL_SD_D1_BAR)
434 #else /* !SDC_HARDCODED_INIT */
435 bl tsi108_sdram_spd /* automatically detect SDC settings */
436 #endif /* SDC_HARDCODED_INIT */
441 LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */
443 LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */
444 #endif /* DISABLE_PBM */
446 #ifdef CONFIG_TSI108EMU
447 oris r5,r5,0x0010 /* set EMULATION_MODE bit */
454 /* Enable SDRAM access */
456 oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */
463 /* wait until SDRAM initialization is complete */
464 beq wait_init_complete
466 /* Map SDRAM into the processor bus address space */
468 ori r4,r29,TSI108_PB_REG_OFFSET
470 /* Setup BARs associated with direct path PB<->SDRAM */
473 * provides a direct path to the main system memory (cacheable SDRAM)
476 /* BA=0,Size=512MB, ENable, No Addr.Translation */
477 LOAD_U32(r5, 0x00000011)
478 stw r5,PB_SDRAM_BAR1(r4)
481 /* Make sure that PB_SDRAM_BAR1 decoder is set
482 * (to allow following immediate read from SDRAM)
484 lwz r5,PB_SDRAM_BAR1(r4)
488 * provides non-cacheable alias (via the direct path) to main
490 * Size = 512MB, ENable, Addr.Translation - ON,
491 * BA = 0x0_40000000, TA = 0x0_00000000
494 LOAD_U32(r5, 0x40010011)
495 stw r5,PB_SDRAM_BAR2(r4)
498 /* Make sure that PB_SDRAM_BAR2 decoder is set
499 * (to allow following immediate read from SDRAM)
501 lwz r5,PB_SDRAM_BAR2(r4)
506 /* All done. Restore LR and return. */
513 * This routine enables CPU1 on the dual-processor system.
514 * Now there is only one processor in the system
520 lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */
521 addi r3,r3,Tsi108_Base@l
522 lwz r3,0(r3) /* R3 = CSR Base Addr */
523 ori r4,r3,TSI108_PB_REG_OFFSET
524 lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
525 ori r3,r3,0x0200 /* Set M1_EN bit */
526 stw r3,PB_ARB_CTRL(r4)
533 * Enable CPU core external interrupt
539 ori r3,r3,0x8000 /* set EE bit */
545 * Disable CPU core external interrupt
551 li r4,-32768 /* aka "li r4,0x8000" */
552 andc r3,r3,r4 /* clear EE bit */
556 #ifdef ENABLE_SDRAM_ECC
557 /* enables SDRAM ECC */
561 ori r4,r29,TSI108_SD_REG_OFFSET
562 lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */
563 ori r3,r3,0x0001 /* Set ECC_EN bit */
564 stw r3,SD_ECC_CTRL(r4)
569 * Clears all pending SDRAM ECC errors
570 * (normally after SDRAM scrubbing/initialization)
573 .global clear_ECC_err
575 ori r4,r29,TSI108_SD_REG_OFFSET
576 ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */
577 stw r3,SD_INT_STATUS(r4)
580 #endif /* ENABLE_SDRAM_ECC */
582 #ifndef SDC_HARDCODED_INIT
584 /* SDRAM SPD Support */
585 #define SD_I2C_CTRL1 (0x400)
586 #define SD_I2C_CTRL2 (0x404)
587 #define SD_I2C_RD_DATA (0x408)
588 #define SD_I2C_WR_DATA (0x40C)
591 * SDRAM SPD Support Macros
594 #define SPD_DIMM0 (0x00000100)
595 #define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */
597 #define SPD_RDIMM (0x01)
598 #define SPD_UDIMM (0x02)
600 #define SPD_CAS_3 0x8
601 #define SPD_CAS_4 0x10
602 #define SPD_CAS_5 0x20
604 #define ERR_NO_DIMM_FOUND (0xdb0)
605 #define ERR_TRAS_FAIL (0xdb1)
606 #define ERR_TRCD_FAIL (0xdb2)
607 #define ERR_TRP_FAIL (0xdb3)
608 #define ERR_TWR_FAIL (0xdb4)
609 #define ERR_UNKNOWN_PART (0xdb5)
610 #define ERR_NRANK_INVALID (0xdb6)
611 #define ERR_DIMM_SIZE (0xdb7)
612 #define ERR_ADDR_MODE (0xdb8)
613 #define ERR_RFRSH_RATE (0xdb9)
614 #define ERR_DIMM_TYPE (0xdba)
615 #define ERR_CL_VALUE (0xdbb)
616 #define ERR_TRFC_FAIL (0xdbc)
618 /* READ_SPD requirements:
619 * byte - byte address in SPD device (0 - 255)
620 * r3 = will return data read from I2C Byte location
621 * r4 - unchanged (SDC base addr)
622 * r5 - clobbered in routine (I2C status)
623 * r10 - number of DDR slot where first SPD device is detected
626 #define READ_SPD(byte_num) \
627 addis r3, 0, byte_num@l; \
630 stw r3, SD_I2C_CTRL1(r4); \
631 li r3, I2C_CNTRL2_START; \
632 stw r3, SD_I2C_CTRL2(r4); \
640 lwz r5, SD_I2C_CTRL2(r4); \
641 rlwinm. r3,r5,0,23,23; \
643 rlwinm. r3,r5,0,3,3; \
644 lwz r3,SD_I2C_RD_DATA(r4)
646 #define SPD_MIN_RFRSH (0x80)
647 #define SPD_MAX_RFRSH (0x85)
649 refresh_rates: /* in nSec */
650 .long 15625 /* Normal (0x80) */
651 .long 3900 /* Reduced 0.25x (0x81) */
652 .long 7800 /* Reduced 0.5x (0x82) */
653 .long 31300 /* Extended 2x (0x83) */
654 .long 62500 /* Extended 4x (0x84) */
655 .long 125000 /* Extended 8x (0x85) */
660 * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
661 * Uses registers: r4 - SDC base address (not changed)
662 * r9 - SDC clocking period in nSec
663 * Changes registers: r3,r5,r6,r7,r8,r10,r11
669 xor r11,r11,r11 /* DIMM Base Address: starts from 0 */
673 /* Program Refresh Rate Register */
675 READ_SPD(12) /* get Refresh Rate */
677 li r5, ERR_RFRSH_RATE
678 cmpi 0,0,r3,SPD_MIN_RFRSH
680 cmpi 0,0,r3,SPD_MAX_RFRSH
682 addi r3,r3,-SPD_MIN_RFRSH
684 lis r5,refresh_rates@h
685 ori r5,r5,refresh_rates@l
686 lwzx r5,r5,r3 /* get refresh rate in nSec */
687 divwu r5,r5,r9 /* calculate # of SDC clocks */
688 stw r5,SD_REFRESH(r4) /* Set refresh rate */
691 /* Program SD Timing Register */
693 li r7, 0 /* clear r7 prior parameter collection */
695 READ_SPD(20) /* get DIMM type: Registered or Unbuffered */
698 cmpi 0,0,r3,SPD_UDIMM
700 cmpi 0,0,r3,SPD_RDIMM
702 oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */
705 READ_SPD(18) /* Get CAS Latency */
708 andi. r6,r3,SPD_CAS_3
713 andi. r6,r3,SPD_CAS_4
718 andi. r6,r3,SPD_CAS_5
724 READ_SPD(30) /* Get tRAS */
733 cmpi 0,0,r6,0x0F /* max supported value */
735 rlwimi r7,r6,16,12,15
737 READ_SPD(29) /* Get tRCD */
739 /* right shift tRCD by 2 bits as per DDR2 spec */
748 cmpi 0,0,r6,0x07 /* max supported value */
750 rlwimi r7,r6,12,17,19
752 READ_SPD(27) /* Get tRP value */
754 rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */
762 cmpi 0,0,r6,0x07 /* max supported value */
766 READ_SPD(36) /* Get tWR value */
768 rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */
775 addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */
777 cmpi 0,0,r6,0x07 /* max supported value */
781 READ_SPD(42) /* Get tRFC */
784 /* Tsi108 spec: tRFC=(tRFC + 1)/2 */
786 rlwinm. r3,r3,31,1,31 /* divide by 2 */
794 cmpi 0,0,r6,0x1F /* max supported value */
802 * The following two registers are set on per-DIMM basis.
803 * The SD_REFRESH and SD_TIMING settings are common for both DIMMS
808 /* Program SDRAM DIMM Control Register */
810 li r7, 0 /* clear r7 prior parameter collection */
812 READ_SPD(13) /* Get Primary SDRAM Width */
814 cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */
816 oris r7,r7,0x0010 /* Set MEM_WIDTH bit */
819 READ_SPD(17) /* Get Number of banks on SDRAM device */
821 /* Grendel only distinguish betw. 4 or 8-bank memory parts */
822 li r5,ERR_UNKNOWN_PART /* non-supported memory part */
830 READ_SPD(5) /* Get # of Ranks */
832 li r5,ERR_NRANK_INVALID
833 andi. r6,r3,0x7 /* Use bits [2..0] only */
840 READ_SPD(4) /* Get # of Column Addresses */
843 andi. r3,r3,0x0f /* cut off reserved bits */
848 addi r6,r3,-8 /* calculate ADDR_MODE parameter */
849 rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */
852 #ifdef SDC_AUTOPRECH_EN
853 oris r7,r7,0x0001 /* set auto precharge EN bit */
855 ori r7,r7,1 /* set ENABLE bit */
856 cmpi 0,0,r10,SPD_DIMM0
858 stw r7,SD_D0_CTRL(r4)
862 stw r7,SD_D1_CTRL(r4)
866 /* Program SDRAM DIMMx Base Address Register */
869 READ_SPD(5) /* get # of Ranks */
873 READ_SPD(31) /* Read DIMM rank density */
875 rlwinm r5,r3,27,29,31
877 or r5,r6,r5 /* r5 = Normalized Rank Density byte */
878 lis r8, 0x0080 /* 128MB >> 4 */
879 mullw r8,r8,r5 /* r8 = (rank_size >> 4) */
880 mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */
883 or r7,r7,r11 /* set ADDR field */
884 rlwinm r8,r8,12,20,31
885 add r11,r11,r8 /* set Base Addr for next DIMM */
887 cmpi 0,0,r10,SPD_DIMM0
903 cmpi 0,0,r10,SPD_DIMM1
913 err_hung: /* hang here for debugging */
918 #endif /* !SDC_HARDCODED_INIT */