1 /*****************************************************************************
2 * (C) Copyright 2003; Tundra Semiconductor Corp.
4 * SPDX-License-Identifier: GPL-2.0+
5 *****************************************************************************/
7 /*----------------------------------------------------------------------------
8 * FILENAME: tsi108_init.c
10 * Originator: Alex Bounine
13 * Initialization code for the Tundra Tsi108 bridge chip
14 *---------------------------------------------------------------------------*/
20 #include <asm/processor.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 extern void mpicInit (int verbose);
28 * Configuration Options
36 PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
38 {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
39 {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
40 {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
41 {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
42 {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
43 {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
44 {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
45 {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
48 {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
49 {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
50 {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
51 {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
52 {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
53 {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
54 {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
55 {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
58 {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
59 {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
60 {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
61 {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
62 {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
63 {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
64 {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
65 {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
67 {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
68 {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
69 {0x00000000, 0x00000241}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap + Translate) */
70 {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */
72 {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
73 {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
74 {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
75 {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
78 #ifdef CONFIG_SYS_CLK_SPREAD
85 * Clock Generator SPLL0 initialization values
86 * PLL0 configuration table for various PB_CLKO freq.
87 * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
88 * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
91 static PLL_CTRL_SET pll0_config[8] = {
92 {0x00000000, 0x00000000}, /* 0: bypass */
93 {0x00000000, 0x00000000}, /* 1: reserved */
94 {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */
95 {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */
96 {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */
97 {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */
98 {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
99 {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
101 #endif /* CONFIG_SYS_CLK_SPREAD */
104 * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
105 * (based on recommended Tsi108 reference clock 33MHz)
107 static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
110 * get_board_bus_clk ()
112 * returns the bus clock in Hz.
114 unsigned long get_board_bus_clk (void)
118 /* Detect PB clock freq. */
119 i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
120 i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
122 return pb_clk_sel[i] * 1000000;
126 * board_early_init_f ()
128 * board-specific initialization executed from flash
131 int board_early_init_f (void)
136 i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
138 i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
140 case 0: /* external clock */
141 printf ("Using external clock\n");
143 case 1: /* system clock */
144 gd->mem_clk = gd->bus_clk;
146 case 4: /* 133 MHz */
147 case 5: /* 166 MHz */
148 case 6: /* 200 MHz */
149 gd->mem_clk = pb_clk_sel[i] * 1000000;
152 printf ("Invalid DDR2 clock setting\n");
155 printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
156 printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
161 * board_early_init_r() - Tsi108 initialization function executed right after
162 * relocation. Contains code that cannot be executed from flash.
165 int board_early_init_r (void)
169 volatile ulong *reg_ptr;
172 (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
174 for (i = 0; i < 32; i++) {
175 *reg_ptr++ = 0x00000201; /* SWAP ENABLED */
179 __asm__ __volatile__ ("eieio");
180 __asm__ __volatile__ ("sync");
182 /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
184 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
186 __asm__ __volatile__ ("sync");
188 /* Make sure that OCN_BAR2 decoder is set (to allow following immediate
192 temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
193 __asm__ __volatile__ ("sync");
196 * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
197 * processor bus address space. Immediately after reset LUT and address
198 * translation are disabled for this BAR. Now we have to initialize LUT
199 * and switch from the BOOT mode to the normal operation mode.
201 * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
202 * and covers 512MB of address space. To allow larger aperture we also
203 * have to relocate register window of Tsi108
205 * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
208 * initialize pointer to LUT associated with PB_OCN_BAR1
211 (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
213 for (i = 0; i < 32; i++) {
214 *reg_ptr++ = pb2ocn_lut1[i].lower;
215 *reg_ptr++ = pb2ocn_lut1[i].upper;
218 __asm__ __volatile__ ("sync");
220 /* Base addresses for CS0, CS1, CS2, CS3 */
222 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
224 __asm__ __volatile__ ("sync");
226 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
228 __asm__ __volatile__ ("sync");
230 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
232 __asm__ __volatile__ ("sync");
234 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
236 __asm__ __volatile__ ("sync");
238 /* Masks for HLP banks */
240 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
242 __asm__ __volatile__ ("sync");
244 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
246 __asm__ __volatile__ ("sync");
248 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
250 __asm__ __volatile__ ("sync");
252 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
254 __asm__ __volatile__ ("sync");
256 /* Set CTRL0 values for banks */
258 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
260 __asm__ __volatile__ ("sync");
262 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
264 __asm__ __volatile__ ("sync");
266 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
268 __asm__ __volatile__ ("sync");
270 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
272 __asm__ __volatile__ ("sync");
274 /* Set banks to latched mode, enabled, and other default settings */
276 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
278 __asm__ __volatile__ ("sync");
280 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
282 __asm__ __volatile__ ("sync");
284 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
286 __asm__ __volatile__ ("sync");
288 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
290 __asm__ __volatile__ ("sync");
293 * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
294 * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
296 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
298 __asm__ __volatile__ ("sync");
300 /* Make sure that OCN_BAR2 decoder is set (to allow following
301 * immediate read from SDRAM)
304 temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
305 __asm__ __volatile__ ("sync");
308 * SRI: At this point we have enabled the HLP banks. That means we can
309 * now read from the NVRAM and initialize the environment variables.
310 * We will over-ride the env_init called in board_init_f
311 * This is really a work-around because, the HLP bank 1
312 * where NVRAM resides is not visible during board_init_f
313 * (arch/powerpc/lib/board.c)
314 * Alternatively, we could use the I2C EEPROM at start-up to configure
315 * and enable all HLP banks and not just HLP 0 as is being done for
324 * For IBM processors we have to set Address-Only commands generated
325 * by PBM that are different from ones set after reset.
328 temp = get_cpu_type ();
330 if ((CPU_750FX == temp) || (CPU_750GX == temp))
331 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
333 #endif /* DISABLE_PBM */
337 * Initialize PCI/X block
340 /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
341 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
342 PCI_PFAB_BAR0_UPPER, 0);
343 __asm__ __volatile__ ("sync");
345 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
347 __asm__ __volatile__ ("sync");
349 /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
351 temp = in32(CONFIG_SYS_TSI108_CSR_BASE +
352 TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
354 temp &= ~0xFF00; /* Clear the BUS_NUM field */
356 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
359 /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
361 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
363 __asm__ __volatile__ ("sync");
365 /* This register is on the PCI side to interpret the address it receives
366 * and maps it as a IO address.
369 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
371 __asm__ __volatile__ ("sync");
374 * Map PCI/X Memory Space
376 * Transactions directed from OCM to PCI Memory Space are directed
378 * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
379 * If address remapping is required the corresponding PCI_PFAB_MEM32
380 * and PCI_PFAB_PFMx register groups have to be configured.
382 * Map the path from the PCI/X bus into the system memory
384 * The memory mapped window assotiated with PCI P2O_BAR2 provides
385 * access to the system memory without address remapping.
386 * All system memory is opened for accesses initiated by PCI/X bus
389 * Initialize LUT associated with PCI P2O_BAR2
391 * set pointer to LUT associated with PCI P2O_BAR2
395 (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
399 /* In case when PBM is disabled (no HW supported cache snoopng on PB)
400 * P2O_BAR2 is directly mapped into the system memory without address
404 reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */
406 for (i = 0; i < 32; i++) {
407 *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
408 *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */
411 /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
412 reg_val = 0x00007500;
415 reg_val = 0x00000002; /* Destination port = PBM */
417 for (i = 0; i < 32; i++) {
418 *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
419 /* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
420 *reg_ptr++ = 0x40000000;
421 /* offset = 16MB, address translation is enabled to allow byte swapping */
422 reg_val += 0x01000000;
425 /* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
426 reg_val = 0x00007100;
429 __asm__ __volatile__ ("eieio");
430 __asm__ __volatile__ ("sync");
432 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
434 __asm__ __volatile__ ("sync");
436 /* Set 64-bit PCI bus address for system memory
437 * ( 0 is the best choice for easy mapping)
440 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
442 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
444 __asm__ __volatile__ ("sync");
448 * The memory mapped window assotiated with PCI P2O_BAR3 provides
449 * access to the system memory using SDRAM OCN port and address
450 * translation. This is alternative way to access SDRAM from PCI
451 * required for Tsi108 emulation testing.
452 * All system memory is opened for accesses initiated by
455 * Initialize LUT associated with PCI P2O_BAR3
457 * set pointer to LUT associated with PCI P2O_BAR3
460 (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
462 reg_val = 0x00000004; /* Destination port = SDC */
464 for (i = 0; i < 32; i++) {
465 *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
467 /* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
470 /* offset = 16MB, address translation is enabled to allow byte swapping */
471 reg_val += 0x01000000;
474 __asm__ __volatile__ ("eieio");
475 __asm__ __volatile__ ("sync");
477 /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
480 in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
484 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
486 __asm__ __volatile__ ("sync");
488 /* Set 64-bit base PCI bus address for window (0x20000000) */
490 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
492 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
494 __asm__ __volatile__ ("sync");
496 #endif /* !DISABLE_PBM */
498 #ifdef ENABLE_PCI_CSR_BAR
499 /* open if required access to Tsi108 CSRs from the PCI/X bus */
500 /* enable BAR0 on the PCI/X bus */
501 reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE +
502 TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
504 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
506 __asm__ __volatile__ ("sync");
508 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
510 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
511 CONFIG_SYS_TSI108_CSR_BASE);
512 __asm__ __volatile__ ("sync");
517 * Finally enable PCI/X Bus Master and Memory Space access
520 reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
522 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
523 __asm__ __volatile__ ("sync");
525 #endif /* CONFIG_PCI */
528 * Initialize MPIC outputs (interrupt pins):
529 * Interrupt routing on the Grendel Emul. Board:
530 * PB_INT[0] -> INT (CPU0)
531 * PB_INT[1] -> INT (CPU1)
532 * PB_INT[2] -> MCP (CPU0)
533 * PB_INT[3] -> MCP (CPU1)
534 * Set interrupt controller outputs as Level_Sensitive/Active_Low
536 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
537 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
538 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
539 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
540 __asm__ __volatile__ ("sync");
543 * Ensure that Machine Check exception is enabled
544 * We need it to support PCI Bus probing (configuration reads)
548 mtmsr(reg_val | MSR_ME);
554 * Needed to print out L2 cache info
555 * used in the misc_init_r function
558 unsigned long get_l2cr (void)
560 unsigned long l2controlreg;
561 asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
568 * various things to do after relocation
572 int misc_init_r (void)
574 #ifdef CONFIG_SYS_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
577 /* Ensure that Spread-Spectrum is disabled */
578 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
579 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
581 /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
582 * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
585 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
586 0x002e0044); /* D = 0.25% */
587 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
588 0x00000039); /* BWADJ */
590 /* Initialize PLL0: CG_PB_CLKO */
591 /* Detect PB clock freq. */
592 i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
593 i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
595 out32 (CONFIG_SYS_TSI108_CSR_BASE +
596 TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
597 out32 (CONFIG_SYS_TSI108_CSR_BASE +
598 TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
600 /* Wait and set SSEN for both PLL0 and 1 */
602 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
603 0x802e0044); /* D=0.25% */
604 out32 (CONFIG_SYS_TSI108_CSR_BASE +
605 TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
606 0x80000000 | pll0_config[i].ctrl0);
607 #endif /* CONFIG_SYS_CLK_SPREAD */
612 printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000);
613 printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
616 * All the information needed to print the cache details is avaiblable
617 * at this point i.e. above call to l2cache_enable is the very last
618 * thing done with regards to enabling diabling the cache.
619 * So this seems like a good place to print all this information
623 switch (get_cpu_type()) {
625 printf ("L1 Instruction cache - 32KB 8-way");
626 (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
627 printf (" DISABLED\n");
628 printf ("L1 Data cache - 32KB 8-way");
629 (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
630 printf (" DISABLED\n");
631 printf ("Unified L2 cache - 512KB 8-way");
632 (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
633 printf (" DISABLED\n");
638 printf ("L1 Instruction cache - 32KB 8-way");
639 (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
640 printf (" DISABLED\n");
641 printf ("L1 Data cache - 32KB 8-way");
642 (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
643 printf (" DISABLED\n");
644 printf ("Unified L2 cache - 1MB 8-way");
645 (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
646 printf (" DISABLED\n");