1 /*****************************************************************************
2 * (C) Copyright 2003; Tundra Semiconductor Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 *****************************************************************************/
20 /*----------------------------------------------------------------------------
21 * FILENAME: tsi108_init.c
23 * Originator: Alex Bounine
26 * Initialization code for the Tundra Tsi108 bridge chip
27 *---------------------------------------------------------------------------*/
33 #include <asm/processor.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 extern void mpicInit (int verbose);
41 * Configuration Options
49 PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
51 {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
52 {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
53 {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
54 {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
55 {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
56 {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
57 {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
58 {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
61 {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
62 {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
63 {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
64 {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
65 {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
66 {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
67 {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
68 {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
71 {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
72 {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
73 {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
74 {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
75 {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
76 {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
77 {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
78 {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
80 {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
81 {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
82 {0x00000000, 0x00000241}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap + Translate) */
83 {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */
85 {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
86 {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
87 {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
88 {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
91 #ifdef CONFIG_SYS_CLK_SPREAD
98 * Clock Generator SPLL0 initialization values
99 * PLL0 configuration table for various PB_CLKO freq.
100 * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
101 * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
104 static PLL_CTRL_SET pll0_config[8] = {
105 {0x00000000, 0x00000000}, /* 0: bypass */
106 {0x00000000, 0x00000000}, /* 1: reserved */
107 {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */
108 {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */
109 {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */
110 {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */
111 {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
112 {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
114 #endif /* CONFIG_SYS_CLK_SPREAD */
117 * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
118 * (based on recommended Tsi108 reference clock 33MHz)
120 static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
123 * get_board_bus_clk ()
125 * returns the bus clock in Hz.
127 unsigned long get_board_bus_clk (void)
131 /* Detect PB clock freq. */
132 i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
133 i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
135 return pb_clk_sel[i] * 1000000;
139 * board_early_init_f ()
141 * board-specific initialization executed from flash
144 int board_early_init_f (void)
149 i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
151 i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
153 case 0: /* external clock */
154 printf ("Using external clock\n");
156 case 1: /* system clock */
157 gd->mem_clk = gd->bus_clk;
159 case 4: /* 133 MHz */
160 case 5: /* 166 MHz */
161 case 6: /* 200 MHz */
162 gd->mem_clk = pb_clk_sel[i] * 1000000;
165 printf ("Invalid DDR2 clock setting\n");
168 printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
169 printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
174 * board_early_init_r() - Tsi108 initialization function executed right after
175 * relocation. Contains code that cannot be executed from flash.
178 int board_early_init_r (void)
182 volatile ulong *reg_ptr;
185 (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
187 for (i = 0; i < 32; i++) {
188 *reg_ptr++ = 0x00000201; /* SWAP ENABLED */
192 __asm__ __volatile__ ("eieio");
193 __asm__ __volatile__ ("sync");
195 /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
197 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
199 __asm__ __volatile__ ("sync");
201 /* Make sure that OCN_BAR2 decoder is set (to allow following immediate
205 temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
206 __asm__ __volatile__ ("sync");
209 * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
210 * processor bus address space. Immediately after reset LUT and address
211 * translation are disabled for this BAR. Now we have to initialize LUT
212 * and switch from the BOOT mode to the normal operation mode.
214 * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
215 * and covers 512MB of address space. To allow larger aperture we also
216 * have to relocate register window of Tsi108
218 * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
221 * initialize pointer to LUT associated with PB_OCN_BAR1
224 (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
226 for (i = 0; i < 32; i++) {
227 *reg_ptr++ = pb2ocn_lut1[i].lower;
228 *reg_ptr++ = pb2ocn_lut1[i].upper;
231 __asm__ __volatile__ ("sync");
233 /* Base addresses for CS0, CS1, CS2, CS3 */
235 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
237 __asm__ __volatile__ ("sync");
239 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
241 __asm__ __volatile__ ("sync");
243 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
245 __asm__ __volatile__ ("sync");
247 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
249 __asm__ __volatile__ ("sync");
251 /* Masks for HLP banks */
253 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
255 __asm__ __volatile__ ("sync");
257 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
259 __asm__ __volatile__ ("sync");
261 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
263 __asm__ __volatile__ ("sync");
265 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
267 __asm__ __volatile__ ("sync");
269 /* Set CTRL0 values for banks */
271 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
273 __asm__ __volatile__ ("sync");
275 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
277 __asm__ __volatile__ ("sync");
279 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
281 __asm__ __volatile__ ("sync");
283 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
285 __asm__ __volatile__ ("sync");
287 /* Set banks to latched mode, enabled, and other default settings */
289 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
291 __asm__ __volatile__ ("sync");
293 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
295 __asm__ __volatile__ ("sync");
297 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
299 __asm__ __volatile__ ("sync");
301 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
303 __asm__ __volatile__ ("sync");
306 * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
307 * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
309 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
311 __asm__ __volatile__ ("sync");
313 /* Make sure that OCN_BAR2 decoder is set (to allow following
314 * immediate read from SDRAM)
317 temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
318 __asm__ __volatile__ ("sync");
321 * SRI: At this point we have enabled the HLP banks. That means we can
322 * now read from the NVRAM and initialize the environment variables.
323 * We will over-ride the env_init called in board_init_f
324 * This is really a work-around because, the HLP bank 1
325 * where NVRAM resides is not visible during board_init_f
326 * (arch/powerpc/lib/board.c)
327 * Alternatively, we could use the I2C EEPROM at start-up to configure
328 * and enable all HLP banks and not just HLP 0 as is being done for
337 * For IBM processors we have to set Address-Only commands generated
338 * by PBM that are different from ones set after reset.
341 temp = get_cpu_type ();
343 if ((CPU_750FX == temp) || (CPU_750GX == temp))
344 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
346 #endif /* DISABLE_PBM */
350 * Initialize PCI/X block
353 /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
354 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
355 PCI_PFAB_BAR0_UPPER, 0);
356 __asm__ __volatile__ ("sync");
358 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
360 __asm__ __volatile__ ("sync");
362 /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
364 temp = in32(CONFIG_SYS_TSI108_CSR_BASE +
365 TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
367 temp &= ~0xFF00; /* Clear the BUS_NUM field */
369 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
372 /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
374 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
376 __asm__ __volatile__ ("sync");
378 /* This register is on the PCI side to interpret the address it receives
379 * and maps it as a IO address.
382 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
384 __asm__ __volatile__ ("sync");
387 * Map PCI/X Memory Space
389 * Transactions directed from OCM to PCI Memory Space are directed
391 * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
392 * If address remapping is required the corresponding PCI_PFAB_MEM32
393 * and PCI_PFAB_PFMx register groups have to be configured.
395 * Map the path from the PCI/X bus into the system memory
397 * The memory mapped window assotiated with PCI P2O_BAR2 provides
398 * access to the system memory without address remapping.
399 * All system memory is opened for accesses initiated by PCI/X bus
402 * Initialize LUT associated with PCI P2O_BAR2
404 * set pointer to LUT associated with PCI P2O_BAR2
408 (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
412 /* In case when PBM is disabled (no HW supported cache snoopng on PB)
413 * P2O_BAR2 is directly mapped into the system memory without address
417 reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */
419 for (i = 0; i < 32; i++) {
420 *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
421 *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */
424 /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
425 reg_val = 0x00007500;
428 reg_val = 0x00000002; /* Destination port = PBM */
430 for (i = 0; i < 32; i++) {
431 *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
432 /* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
433 *reg_ptr++ = 0x40000000;
434 /* offset = 16MB, address translation is enabled to allow byte swapping */
435 reg_val += 0x01000000;
438 /* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
439 reg_val = 0x00007100;
442 __asm__ __volatile__ ("eieio");
443 __asm__ __volatile__ ("sync");
445 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
447 __asm__ __volatile__ ("sync");
449 /* Set 64-bit PCI bus address for system memory
450 * ( 0 is the best choice for easy mapping)
453 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
455 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
457 __asm__ __volatile__ ("sync");
461 * The memory mapped window assotiated with PCI P2O_BAR3 provides
462 * access to the system memory using SDRAM OCN port and address
463 * translation. This is alternative way to access SDRAM from PCI
464 * required for Tsi108 emulation testing.
465 * All system memory is opened for accesses initiated by
468 * Initialize LUT associated with PCI P2O_BAR3
470 * set pointer to LUT associated with PCI P2O_BAR3
473 (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
475 reg_val = 0x00000004; /* Destination port = SDC */
477 for (i = 0; i < 32; i++) {
478 *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
480 /* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
483 /* offset = 16MB, address translation is enabled to allow byte swapping */
484 reg_val += 0x01000000;
487 __asm__ __volatile__ ("eieio");
488 __asm__ __volatile__ ("sync");
490 /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
493 in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
497 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
499 __asm__ __volatile__ ("sync");
501 /* Set 64-bit base PCI bus address for window (0x20000000) */
503 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
505 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
507 __asm__ __volatile__ ("sync");
509 #endif /* !DISABLE_PBM */
511 #ifdef ENABLE_PCI_CSR_BAR
512 /* open if required access to Tsi108 CSRs from the PCI/X bus */
513 /* enable BAR0 on the PCI/X bus */
514 reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE +
515 TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
517 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
519 __asm__ __volatile__ ("sync");
521 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
523 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
524 CONFIG_SYS_TSI108_CSR_BASE);
525 __asm__ __volatile__ ("sync");
530 * Finally enable PCI/X Bus Master and Memory Space access
533 reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
535 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
536 __asm__ __volatile__ ("sync");
538 #endif /* CONFIG_PCI */
541 * Initialize MPIC outputs (interrupt pins):
542 * Interrupt routing on the Grendel Emul. Board:
543 * PB_INT[0] -> INT (CPU0)
544 * PB_INT[1] -> INT (CPU1)
545 * PB_INT[2] -> MCP (CPU0)
546 * PB_INT[3] -> MCP (CPU1)
547 * Set interrupt controller outputs as Level_Sensitive/Active_Low
549 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
550 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
551 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
552 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
553 __asm__ __volatile__ ("sync");
556 * Ensure that Machine Check exception is enabled
557 * We need it to support PCI Bus probing (configuration reads)
561 mtmsr(reg_val | MSR_ME);
567 * Needed to print out L2 cache info
568 * used in the misc_init_r function
571 unsigned long get_l2cr (void)
573 unsigned long l2controlreg;
574 asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
581 * various things to do after relocation
585 int misc_init_r (void)
587 #ifdef CONFIG_SYS_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
590 /* Ensure that Spread-Spectrum is disabled */
591 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
592 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
594 /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
595 * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
598 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
599 0x002e0044); /* D = 0.25% */
600 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
601 0x00000039); /* BWADJ */
603 /* Initialize PLL0: CG_PB_CLKO */
604 /* Detect PB clock freq. */
605 i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
606 i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
608 out32 (CONFIG_SYS_TSI108_CSR_BASE +
609 TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
610 out32 (CONFIG_SYS_TSI108_CSR_BASE +
611 TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
613 /* Wait and set SSEN for both PLL0 and 1 */
615 out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
616 0x802e0044); /* D=0.25% */
617 out32 (CONFIG_SYS_TSI108_CSR_BASE +
618 TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
619 0x80000000 | pll0_config[i].ctrl0);
620 #endif /* CONFIG_SYS_CLK_SPREAD */
625 printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000);
626 printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
629 * All the information needed to print the cache details is avaiblable
630 * at this point i.e. above call to l2cache_enable is the very last
631 * thing done with regards to enabling diabling the cache.
632 * So this seems like a good place to print all this information
636 switch (get_cpu_type()) {
638 printf ("L1 Instruction cache - 32KB 8-way");
639 (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
640 printf (" DISABLED\n");
641 printf ("L1 Data cache - 32KB 8-way");
642 (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
643 printf (" DISABLED\n");
644 printf ("Unified L2 cache - 512KB 8-way");
645 (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
646 printf (" DISABLED\n");
651 printf ("L1 Instruction cache - 32KB 8-way");
652 (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
653 printf (" DISABLED\n");
654 printf ("L1 Data cache - 32KB 8-way");
655 (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
656 printf (" DISABLED\n");
657 printf ("Unified L2 cache - 1MB 8-way");
658 (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
659 printf (" DISABLED\n");