2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
12 * (C) Copyright 2003-2004 Arabella Software Ltd.
13 * Yuli Barcohen <yuli@arabellasw.com>
14 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
16 * Copyright (c) 2005 MontaVista Software, Inc.
17 * Vitaly Bordug <vbordug@ru.mvista.com>
18 * Added support for PCI.
20 * SPDX-License-Identifier: GPL-2.0+
26 #include <asm/m8260_pci.h>
33 #ifdef CONFIG_OF_LIBFDT
35 #include <fdt_support.h>
39 * I/O Port configuration table
41 * if conf is 1, then that port pin will be configured at boot time
42 * according to the five values podr/pdir/ppar/psor/pdat for that entry
45 #define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
46 #define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
47 #define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
49 const iop_conf_t iop_conf_tab[4][32] = {
51 /* Port A configuration */
52 { /* conf ppar psor pdir podr pdat */
53 /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
54 /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
55 /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
56 /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
57 /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
58 /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
59 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
60 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
61 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
62 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
63 /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
64 /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
65 /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
66 /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
67 /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
68 /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
69 /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
70 /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
71 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
72 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
73 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
74 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
75 /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
76 /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
77 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
78 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
79 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
80 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
81 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
82 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
83 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
84 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
87 /* Port B configuration */
88 { /* conf ppar psor pdir podr pdat */
89 /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
90 /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
91 /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
92 /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
93 /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
94 /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
95 /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
96 /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
97 /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
98 /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
99 /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
100 /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
101 /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
102 /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
103 /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
104 /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
105 /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
106 /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
107 /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
108 /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
109 /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
110 /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
111 /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
114 /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
115 /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
118 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
119 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
120 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
124 { /* conf ppar psor pdir podr pdat */
125 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
126 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
127 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
128 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
129 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
130 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
131 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
132 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
133 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
134 /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
135 /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
136 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
137 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
138 /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
139 /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
140 /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
141 /* PC16 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
143 /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
144 /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
145 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
146 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
147 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
148 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
149 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
150 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
151 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
152 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
153 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
154 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
155 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
157 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
158 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
159 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
160 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
161 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
162 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
163 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
164 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
165 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
166 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
167 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
168 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
172 { /* conf ppar psor pdir podr pdat */
173 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
174 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
175 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
176 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
177 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
178 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
179 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
180 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
181 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
182 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
183 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
184 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
185 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
186 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
187 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
188 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
189 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
190 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
191 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
192 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
193 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
194 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
195 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
196 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
197 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
198 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
199 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
200 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
201 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
202 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
203 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
204 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
208 void reset_phy (void)
210 vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
213 #if CONFIG_SYS_PHY_ADDR == 0
214 bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
216 bcsr[1] |= FETH1_RST;
218 bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
220 bcsr[3] |= FETH2_RST;
221 #endif /* CONFIG_SYS_PHY_ADDR == 0 */
224 #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
226 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
227 * Enable autonegotiation.
229 bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610);
230 bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
231 BMCR_ANENABLE | BMCR_ANRESTART);
234 * Ethernet PHY is configured (by means of configuration pins)
235 * to work at 10Mb/s only. We reconfigure it using MII
236 * to advertise all capabilities, including 100Mb/s, and
237 * restart autonegotiation.
240 /* Advertise all capabilities */
241 bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1);
243 /* Do not bypass Rx/Tx (de)scrambler */
244 bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER, 0x0000);
246 bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
247 BMCR_ANENABLE | BMCR_ANRESTART);
248 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
249 #endif /* CONFIG_MII */
253 typedef struct pci_ic_s {
254 unsigned long pci_int_stat;
255 unsigned long pci_int_mask;
259 int board_early_init_f (void)
261 vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
264 volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
266 /* mask alll the PCI interrupts */
267 pci_ic->pci_int_mask |= 0xfff00000;
269 #if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
270 bcsr[1] &= ~RS232EN_1;
272 #if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
273 bcsr[1] &= ~RS232EN_2;
276 #if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */
277 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
278 if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
279 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
281 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
283 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
284 immap->im_siu_conf.sc_siumcr =
285 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
288 #endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */
293 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
295 phys_size_t initdram (int board_type)
297 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
299 #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
305 #ifndef CONFIG_SYS_RAMBOOT
306 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
307 volatile memctl8260_t *memctl = &immap->im_memctl;
308 volatile uchar *ramaddr, c = 0xff;
315 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
316 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
317 immap->im_siu_conf.sc_tescr1 = 0x00004000;
319 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
320 #ifdef CONFIG_SYS_LSDRAM_BASE
322 Initialise local bus SDRAM only if the pins
323 are configured as local bus pins and not as PCI.
324 The configuration is determined by the HRCW.
326 if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
327 memctl->memc_lsrt = CONFIG_SYS_LSRT;
328 #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */
329 memctl->memc_or3 = 0xFF803280;
330 memctl->memc_br3 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
332 memctl->memc_or4 = 0xFFC01480;
333 memctl->memc_br4 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
334 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
335 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
336 ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE;
338 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
339 for (i = 0; i < 8; i++)
341 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
343 memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
345 #endif /* CONFIG_SYS_LSDRAM_BASE */
347 /* Init 60x bus SDRAM */
348 #ifdef CONFIG_SPD_EEPROM
351 uint pbi, bsel, rowst, lsb, tmp;
353 i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
355 /* Bank-based interleaving is not supported for physical bank
356 sizes greater than 128MB which is encoded as 0x20 in SPD
358 pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
359 msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
360 or = ~(msize - 1) << 20; /* SDAM */
361 switch (spd.nbanks) { /* BPD */
374 lsb = 3; /* For 64-bit port, lsb is 3 bits */
376 if (pbi) { /* Bus partition depends on interleaving */
377 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
378 or |= (rowst << 9); /* ROWST */
380 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
381 or |= ((rowst * 2 - 12) << 9); /* ROWST */
383 or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
385 psdmr = (pbi << 31); /* PBI */
386 /* Bus multiplexing parameters */
387 tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
388 psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
389 psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
391 tmp = (31 - lsb - 10) - tmp;
392 /* Pin connected to SDA10 is (31 - lsb - 10).
393 rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
394 so (rowst + tmp) alternates with AP.
396 if (pbi) /* Table 10-7 */
397 psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
399 psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
401 /* SDRAM device-specific parameters */
402 tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
403 switch (tmp) { /* RFRC */
414 psdmr |= ((tmp - 2) << 15);
419 psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
420 psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
421 /* BL=0 because for 64-bit SDRAM burst length must be 4 */
423 for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
425 switch (i) { /* WRC */
435 /* EAMUX=0 - no external address multiplexing */
436 /* BUFCMD=0 - no external buffers */
437 for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
441 switch (spd.refresh & 0x7F) {
460 psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
461 ((memctl->memc_mptpr >> 8) + 1)) - 1;
463 printf ("\nDIMM type: %-18.18s\n", spd.mpart);
464 printf ("SPD size: %d\n", spd.info_size);
465 printf ("EEPROM size: %d\n", 1 << spd.chip_size);
466 printf ("Memory type: %d\n", spd.mem_type);
467 printf ("Row addr: %d\n", spd.nrow_addr);
468 printf ("Column addr: %d\n", spd.ncol_addr);
469 printf ("# of rows: %d\n", spd.nrows);
470 printf ("Row density: %d\n", spd.row_dens);
471 printf ("# of banks: %d\n", spd.nbanks);
472 printf ("Data width: %d\n",
473 256 * spd.dataw_msb + spd.dataw_lsb);
474 printf ("Chip width: %d\n", spd.primw);
475 printf ("Refresh rate: %02X\n", spd.refresh);
476 printf ("CAS latencies: %02X\n", spd.cas_lat);
477 printf ("Write latencies: %02X\n", spd.write_lat);
478 printf ("tRP: %d\n", spd.trp);
479 printf ("tRCD: %d\n", spd.trcd);
481 printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
482 #endif /* SPD_DEBUG */
484 #else /* !CONFIG_SPD_EEPROM */
486 psdmr = CONFIG_SYS_PSDMR;
487 psrt = CONFIG_SYS_PSRT;
488 #endif /* CONFIG_SPD_EEPROM */
489 memctl->memc_psrt = psrt;
490 memctl->memc_or2 = or;
491 memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041;
492 ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
493 memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
495 memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
496 for (i = 0; i < 8; i++)
499 memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
501 memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
503 #endif /* CONFIG_SYS_RAMBOOT */
505 /* return total 60x bus SDRAM size */
506 return (msize * 1024 * 1024);
509 int checkboard (void)
511 #if CONFIG_ADSTYPE == CONFIG_SYS_8260ADS
512 puts ("Board: Motorola MPC8260ADS\n");
513 #elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS
514 puts ("Board: Motorola MPC8266ADS\n");
515 #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
516 puts ("Board: Motorola PQ2FADS-ZU\n");
517 #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
518 puts ("Board: Motorola MPC8272ADS\n");
520 puts ("Board: unknown\n");
526 struct pci_controller hose;
528 extern void pci_mpc8250_init(struct pci_controller *);
530 void pci_init_board(void)
532 pci_mpc8250_init(&hose);
536 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
537 void ft_board_setup(void *blob, bd_t *bd)
539 ft_cpu_setup(blob, bd);
541 ft_pci_setup(blob, bd);